OV - - Loop 33

	Loop Id: 33	Module: exec	Source: haloExchange.c:380-390	Coverage: 0.11%

0x407260 VADDSD	(%RCX),%XMM4,%XMM0    [7]

0x407264 MOV	(%R11,%RSI,4),%R15D    [4]

0x407268 INC	%EDI

0x40726a ADD	$0x38,%RAX

0x40726e ADD	$0x18,%RCX

0x407272 ADD	$0x18,%RDX

0x407276 MOV	%R15D,-0x38(%RAX)    [1]

0x40727a MOV	(%R10,%RSI,4),%R15D    [3]

0x40727e INC	%RSI

0x407281 VMOVSD	%XMM0,-0x30(%RAX)    [1]

0x407286 VADDSD	-0x10(%RCX),%XMM5,%XMM7    [5]

0x40728b MOV	%R15D,-0x34(%RAX)    [1]

0x40728f MOV	(%R8),%R15D    [6]

0x407292 VMOVSD	%XMM7,-0x28(%RAX)    [1]

0x407297 VADDSD	-0x8(%RCX),%XMM6,%XMM8    [5]

0x40729c ADD	%R9D,%R15D

0x40729f VMOVSD	%XMM8,-0x20(%RAX)    [1]

0x4072a4 VMOVSD	-0x18(%RDX),%XMM9    [2]

0x4072a9 VMOVSD	%XMM9,-0x18(%RAX)    [1]

0x4072ae VMOVSD	-0x10(%RDX),%XMM10    [2]

0x4072b3 VMOVSD	%XMM10,-0x10(%RAX)    [1]

0x4072b8 VMOVSD	-0x8(%RDX),%XMM11    [2]

0x4072bd VMOVSD	%XMM11,-0x8(%RAX)    [1]

0x4072c2 CMP	%ESI,%R15D

0x4072c5 JG	407260

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 380 - 390

--------------------------------------------------------------------------------

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

390:          ++nBuf;

Path /

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	6.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P5, P6, P7,
Function	loadAtomsBuffer
Source	haloExchange.c:380-390
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	4.79
CQA cycles if fully vectorized	0.92
Front-end cycles	4.00
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	24.00
Nb loads	9.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.53
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.47
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	10.94
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	6.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.42
Bottlenecks	P5, P6, P7,
Function	loadAtomsBuffer
Source	haloExchange.c:380-390
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.67
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	4.79
CQA cycles if fully vectorized	0.92
Front-end cycles	4.00
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	24.00
Nb loads	9.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.53
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.47
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	10.94
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	loadAtomsBuffer
Source file and lines	haloExchange.c:380-390
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:380-390.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.67 to 5.00 cycles (1.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.67 to 0.92 cycles (6.18x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.67 to 4.00 cycles (1.42x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	25
nb uops	24
loop length	103
used x86 registers	10
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	5.67	5.67	5.67	0.00	0.00	1.50	1.50	3.00	3.00
cycles	1.75	1.75	1.50	1.50	0.50	5.67	5.67	5.67	0.00	0.00	1.50	1.50	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.00
Dispatch	5.67
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

11% of peak load performance is reached (10.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.88 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 407260

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VADDSD (%RCX),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
MOV (%R11,%RSI,4),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x38,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,-0x38(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%R10,%RSI,4),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,-0x30(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VADDSD -0x10(%RCX),%XMM5,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
MOV %R15D,-0x34(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%R8),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD %XMM7,-0x28(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VADDSD -0x8(%RCX),%XMM6,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
ADD %R9D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM8,-0x20(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x18(%RDX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM9,-0x18(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RDX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM10,-0x10(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RDX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM11,-0x8(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %ESI,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JG 407260 <loadAtomsBuffer+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	loadAtomsBuffer
Source file and lines	haloExchange.c:380-390
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.67 to 5.00 cycles (1.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.67 to 4.00 cycles (1.42x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	25
nb uops	24
loop length	103
used x86 registers	10
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	5.67	5.67	5.67	0.00	0.00	1.50	1.50	3.00	3.00
cycles	1.75	1.75	1.50	1.50	0.50	5.67	5.67	5.67	0.00	0.00	1.50	1.50	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.00
Dispatch	5.67
Data deps.	1.00
Overall L1	5.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.67 cycles. At this rate:

11% of peak load performance is reached (10.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.88 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 407260

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VADDSD (%RCX),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
MOV (%R11,%RSI,4),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x38,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,-0x38(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%R10,%RSI,4),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,-0x30(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VADDSD -0x10(%RCX),%XMM5,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
MOV %R15D,-0x34(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%R8),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD %XMM7,-0x28(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VADDSD -0x8(%RCX),%XMM6,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
ADD %R9D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM8,-0x20(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x18(%RDX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM9,-0x18(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RDX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM10,-0x10(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RDX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD %XMM11,-0x8(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %ESI,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JG 407260 <loadAtomsBuffer+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	0.5	0.04	0.33	0.03

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.34	0.11
2x2	2	1	2	2	0.36	0.11
2x4	2	1	4	4	0.34	0.11
2x8	2	1	8	8	0.35	0.1
2x16	2	1	16	16	0.33	0.1
2x32	2	1	32	32	0.36	0.08
2x64	2	0.5	32	64	0.36	0.07
2x96	2	0.33	32	96	0.38	0.05

Report Configuration

Code clean check

Workaround

Vectorization

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Execution units bottlenecks

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Slow data structures access

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

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General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency