OV - - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:45-75 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 75

--------------------------------------------------------------------------------

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

[...]

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

75: }

0x40ef10 MOV	$0x613606df9756715,%R8

0x40ef1a IMUL	$-0x61c8864f,%EDI,%ECX

0x40ef20 ADD	%ESI,%EDI

0x40ef22 MOV	$0x9,%ESI

0x40ef27 IMUL	$-0x61c8864f,%EDI,%EDI

0x40ef2d SAL	$0x20,%RCX

0x40ef31 ADD	%RDI,%RCX

0x40ef34 IMUL	%R8,%RCX

0x40ef38 MOV	%RCX,%RAX

0x40ef3b MOV	%RCX,%R9

0x40ef3e MUL	%RSI

0x40ef41 SUB	%RDX,%R9

0x40ef44 SHR	$0x1,%R9

0x40ef47 ADD	%R9,%RDX

0x40ef4a SHR	$0x3c,%RDX

0x40ef4e MOV	%RDX,%R10

0x40ef51 SAL	$0x3d,%R10

0x40ef55 SUB	%RDX,%R10

0x40ef58 SUB	%R10,%RCX

0x40ef5b IMUL	%R8,%RCX

0x40ef5f MOV	%RCX,%RAX

0x40ef62 MOV	%RCX,%R11

0x40ef65 MUL	%RSI

0x40ef68 SUB	%RDX,%R11

0x40ef6b SHR	$0x1,%R11

0x40ef6e ADD	%R11,%RDX

0x40ef71 SHR	$0x3c,%RDX

0x40ef75 MOV	%RDX,%RDI

0x40ef78 SAL	$0x3d,%RDI

0x40ef7c SUB	%RDX,%RDI

0x40ef7f SUB	%RDI,%RCX

0x40ef82 IMUL	%R8,%RCX

0x40ef86 MOV	%RCX,%RAX

0x40ef89 MOV	%RCX,%R9

0x40ef8c MUL	%RSI

0x40ef8f SUB	%RDX,%R9

0x40ef92 SHR	$0x1,%R9

0x40ef95 ADD	%R9,%RDX

0x40ef98 SHR	$0x3c,%RDX

0x40ef9c MOV	%RDX,%R10

0x40ef9f SAL	$0x3d,%R10

0x40efa3 SUB	%RDX,%R10

0x40efa6 SUB	%R10,%RCX

0x40efa9 IMUL	%R8,%RCX

0x40efad MOV	%RCX,%RAX

0x40efb0 MOV	%RCX,%R11

0x40efb3 MUL	%RSI

0x40efb6 SUB	%RDX,%R11

0x40efb9 SHR	$0x1,%R11

0x40efbc ADD	%R11,%RDX

0x40efbf SHR	$0x3c,%RDX

0x40efc3 MOV	%RDX,%RDI

0x40efc6 SAL	$0x3d,%RDI

0x40efca SUB	%RDX,%RDI

0x40efcd SUB	%RDI,%RCX

0x40efd0 IMUL	%R8,%RCX

0x40efd4 MOV	%RCX,%RAX

0x40efd7 MOV	%RCX,%R9

0x40efda MUL	%RSI

0x40efdd SUB	%RDX,%R9

0x40efe0 SHR	$0x1,%R9

0x40efe3 ADD	%R9,%RDX

0x40efe6 SHR	$0x3c,%RDX

0x40efea MOV	%RDX,%R10

0x40efed SAL	$0x3d,%R10

0x40eff1 SUB	%RDX,%R10

0x40eff4 SUB	%R10,%RCX

0x40eff7 IMUL	%R8,%RCX

0x40effb MOV	%RCX,%RAX

0x40effe MOV	%RCX,%R11

0x40f001 MUL	%RSI

0x40f004 SUB	%RDX,%R11

0x40f007 SHR	$0x1,%R11

0x40f00a ADD	%R11,%RDX

0x40f00d SHR	$0x3c,%RDX

0x40f011 MOV	%RDX,%RDI

0x40f014 SAL	$0x3d,%RDI

0x40f018 SUB	%RDX,%RDI

0x40f01b SUB	%RDI,%RCX

0x40f01e IMUL	%R8,%RCX

0x40f022 MOV	%RCX,%RAX

0x40f025 MOV	%RCX,%R9

0x40f028 MUL	%RSI

0x40f02b SUB	%RDX,%R9

0x40f02e SHR	$0x1,%R9

0x40f031 ADD	%R9,%RDX

0x40f034 SHR	$0x3c,%RDX

0x40f038 MOV	%RDX,%R10

0x40f03b SAL	$0x3d,%R10

0x40f03f SUB	%RDX,%R10

0x40f042 SUB	%R10,%RCX

0x40f045 IMUL	%R8,%RCX

0x40f049 MOV	%RCX,%RAX

0x40f04c MOV	%RCX,%R11

0x40f04f MUL	%RSI

0x40f052 SUB	%RDX,%R11

0x40f055 SHR	$0x1,%R11

0x40f058 ADD	%R11,%RDX

0x40f05b SHR	$0x3c,%RDX

0x40f05f MOV	%RDX,%RDI

0x40f062 SAL	$0x3d,%RDI

0x40f066 SUB	%RDX,%RDI

0x40f069 SUB	%RDI,%RCX

0x40f06c IMUL	%R8,%RCX

0x40f070 MOV	%RCX,%RAX

0x40f073 MOV	%RCX,%R9

0x40f076 MUL	%RSI

0x40f079 SUB	%RDX,%R9

0x40f07c SHR	$0x1,%R9

0x40f07f ADD	%R9,%RDX

0x40f082 SHR	$0x3c,%RDX

0x40f086 MOV	%RDX,%R10

0x40f089 SAL	$0x3d,%R10

0x40f08d SUB	%RDX,%R10

0x40f090 SUB	%R10,%RCX

0x40f093 IMUL	%R8,%RCX

0x40f097 MOV	%RCX,%RAX

0x40f09a MOV	%RCX,%R8

0x40f09d MUL	%RSI

0x40f0a0 MOV	%RCX,%RAX

0x40f0a3 SUB	%RDX,%R8

0x40f0a6 SHR	$0x1,%R8

0x40f0a9 ADD	%R8,%RDX

0x40f0ac SHR	$0x3c,%RDX

0x40f0b0 MOV	%RDX,%RSI

0x40f0b3 SAL	$0x3d,%RSI

0x40f0b7 SUB	%RDX,%RSI

0x40f0ba SUB	%RSI,%RAX

0x40f0bd RET

0x40f0be XCHG	%AX,%AX

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	random.c:45-75
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 32.00 to 3.87 cycles (8.26x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.00 cycles. At this rate:

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40ef10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	Latency	Recip. throughput
MOV $0x613606df9756715,%R8	1	0.25	0.25	0.25	0.25	0	1	0.33
IMUL $-0x61c8864f,%EDI,%ECX	1	0	1	0	0	0	3	1
ADD %ESI,%EDI	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV $0x9,%ESI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL $-0x61c8864f,%EDI,%EDI	1	0	1	0	0	0	3	1
SAL $0x20,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R8	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SUB %RDX,%R8	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R8	1	0	0.50	0.50	0	0	1	0.50
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RSI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RSI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
RET	1	0.50	0	0	0	0.50	1	0.50

Source file and lines	random.c:45-75
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.00 cycles. At this rate:

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40ef10

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	Latency	Recip. throughput
MOV $0x613606df9756715,%R8	1	0.25	0.25	0.25	0.25	0	1	0.33
IMUL $-0x61c8864f,%EDI,%ECX	1	0	1	0	0	0	3	1
ADD %ESI,%EDI	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV $0x9,%ESI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL $-0x61c8864f,%EDI,%EDI	1	0	1	0	0	0	3	1
SAL $0x20,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R11	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R11	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R11	1	0	0.50	0.50	0	0	1	0.50
ADD %R11,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RDI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RDI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R9	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
SUB %RDX,%R9	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R9	1	0	0.50	0.50	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%R10	1	0	0	0	0	0	0	0.17
SAL $0x3d,%R10	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%R10	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %R10,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %R8,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MOV %RCX,%R8	1	0	0	0	0	0	0	0.17
MUL %RSI	2	0	2	0	0	0	3-4	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SUB %RDX,%R8	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%R8	1	0	0.50	0.50	0	0	1	0.50
ADD %R8,%RDX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	1	0.50
MOV %RDX,%RSI	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RSI	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SUB %RSI,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
RET	1	0.50	0	0	0	0.50	1	0.50

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	0.5	0.01	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.05	0.01
2x2	4	1	2	2	0.03	0.02
2x4	8	1	4	4	0.02	0.02
2x8	16	0.5	4	8	0.02	0.02
2x16	32	1	1	16	0.02	0.02
2x32	64	1	1	32	0.01	0.01
2x64	122	1	1	64	0.01	0.01
2x96	164	1	1	96	0	0.01

Name	Coverage (%)	Time (s)
○mkSeed	0.01	0.04

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency