OV - - Function lcg61

	Function: lcg61	Module: exec	Source: random.c:42-49	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 42 - 49

--------------------------------------------------------------------------------

42: {

43:    static const double convertToDouble = 1.0/UINT64_C(2305843009213693951);

44:

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

49: }

0x40eec0 MOV	$0x9,%EAX

0x40eec5 MOV	%RDI,%RSI

0x40eec8 VXORPS	%XMM0,%XMM0,%XMM0

0x40eecc MOV	$0x613606df9756715,%RCX

0x40eed6 IMUL	(%RDI),%RCX

0x40eeda MUL	%RCX

0x40eedd MOV	%RCX,%RDI

0x40eee0 SUB	%RDX,%RDI

0x40eee3 SHR	$0x1,%RDI

0x40eee6 ADD	%RDI,%RDX

0x40eee9 SHR	$0x3c,%RDX

0x40eeed MOV	%RDX,%R8

0x40eef0 SAL	$0x3d,%R8

0x40eef4 SUB	%RDX,%R8

0x40eef7 SUB	%R8,%RCX

0x40eefa VCVTSI2SD	%RCX,%XMM0,%XMM1

0x40eeff MOV	%RCX,(%RSI)

0x40ef02 VMULSD	0x3ade(%RIP),%XMM1,%XMM0

0x40ef0a RET

0x40ef0b NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	random.c:42-49
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:42-49.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.67 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.31 cycles (11.20x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 1 occurrences
VCVTSI2SD: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 16 bytes (2 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	19
nb uops	21
loop length	75
used x86 registers	6
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.25	3.25	3.00	3.00	0.50	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	3.25	3.25	3.00	3.00	0.50	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.25
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

4% of peak load performance is reached (4.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 3.25 cycles (1.08x speedup).

ASM code

In the binary file, the address of the function is: 40eec0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
MOV $0x9,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x613606df9756715,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33
IMUL (%RDI),%RCX	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
MUL %RCX	2	0	2	0	0	0	0	0	0	0	0	0	0	3-4	1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x1,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %RCX,%XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1.25
MOV %RCX,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMULSD 0x3ade(%RIP),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50

Source file and lines	random.c:42-49
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:42-49.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.67 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 1 occurrences
VCVTSI2SD: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 16 bytes (2 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	19
nb uops	21
loop length	75
used x86 registers	6
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.25	3.25	3.00	3.00	0.50	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	3.25	3.25	3.00	3.00	0.50	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Dispatch	3.25
Overall L1	3.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

4% of peak load performance is reached (4.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40eec0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
MOV $0x9,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x613606df9756715,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33
IMUL (%RDI),%RCX	1	0	1	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
MUL %RCX	2	0	2	0	0	0	0	0	0	0	0	0	0	3-4	1
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x1,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD %RDI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3c,%RDX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3d,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB %RDX,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SUB %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %RCX,%XMM0,%XMM1	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1.25
MOV %RCX,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
VMULSD 0x3ade(%RIP),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	2	0	1	0	0.5	0.01	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.01
2x2	4	2	4	2	0.02	0.01
2x4	8	1	4	4	0.01	0.01
2x8	16	0.5	4	8	0.01	0.01
2x16	22	1	1	16	0	0.01
2x32	26	1	1	32	0	0.01
2x64	29	1	1	64	0	0.01
2x96	66	1	1	96	0	0.01

Name	Coverage (%)	Time (s)
○lcg61	0.01	0.04

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency