OV - - Function moveAtom

	Function: moveAtom	Module: exec	Source: linkCells.c:257-335 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 257 - 335

--------------------------------------------------------------------------------

257: {

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

270:

271:    return;

272: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

335: }

0x40afd0 PUSH	%RBP

0x40afd1 MOVSXD	%ECX,%R9

0x40afd4 MOV	%RSI,%RAX

0x40afd7 MOV	%RDI,%R11

0x40afda MOV	%R8D,%ECX

0x40afdd SAL	$0x6,%ECX

0x40afe0 MOV	%RSP,%RBP

0x40afe3 PUSH	%R13

0x40afe5 PUSH	%R12

0x40afe7 MOV	%R9D,%R12D

0x40afea PUSH	%RBX

0x40afeb SAL	$0x6,%R12D

0x40afef MOVSXD	%R8D,%RBX

0x40aff2 ADD	%R12D,%EDX

0x40aff5 MOVSXD	%EDX,%RDX

0x40aff8 SUB	$0x8,%RSP

0x40affc MOV	0x78(%RDI),%RDI

0x40b000 MOV	0x8(%RSI),%RSI

0x40b004 MOV	0x10(%RAX),%R13

0x40b008 MOV	(%RSI,%RDX,4),%R10D

0x40b00c ADD	(%RDI,%RBX,4),%ECX

0x40b00f LEA	(%RDX,%RDX,2),%RDI

0x40b013 MOVSXD	%ECX,%RCX

0x40b016 SAL	$0x3,%RDI

0x40b01a MOV	%R10D,(%RSI,%RCX,4)

0x40b01e MOV	(%R13,%RDX,4),%ESI

0x40b023 MOV	0x18(%RAX),%R10

0x40b027 MOV	%ESI,(%R13,%RCX,4)

0x40b02c LEA	(%RCX,%RCX,2),%RSI

0x40b030 SAL	$0x3,%RSI

0x40b034 LEA	(%R10,%RSI,1),%R13

0x40b038 ADD	%RDI,%R10

0x40b03b VMOVDQU	(%R10),%XMM0

0x40b040 VMOVDQU	%XMM0,(%R13)

0x40b046 MOV	0x10(%R10),%R10

0x40b04a MOV	%R10,0x10(%R13)

0x40b04e MOV	0x20(%RAX),%R10

0x40b052 LEA	(%R10,%RSI,1),%R13

0x40b056 ADD	%RDI,%R10

0x40b059 VMOVDQU	(%R10),%XMM1

0x40b05e VMOVDQU	%XMM1,(%R13)

0x40b064 MOV	0x10(%R10),%R10

0x40b068 MOV	%R10,0x10(%R13)

0x40b06c MOV	0x28(%RAX),%R13

0x40b070 ADD	%R13,%RSI

0x40b073 ADD	%RDI,%R13

0x40b076 VMOVDQU	(%R13),%XMM2

0x40b07c VMOVDQU	%XMM2,(%RSI)

0x40b080 MOV	0x10(%R13),%R10

0x40b084 MOV	%R10,0x10(%RSI)

0x40b088 MOV	0x30(%RAX),%RSI

0x40b08c MOV	(%RSI,%RDX,8),%R13

0x40b090 MOV	%R13,(%RSI,%RCX,8)

0x40b094 MOV	0x78(%R11),%R10

0x40b098 LEA	(%R10,%RBX,4),%RSI

0x40b09c MOV	(%RSI),%EBX

0x40b09e LEA	0x1(%RBX),%ECX

0x40b0a1 MOV	%ECX,(%RSI)

0x40b0a3 CMP	$0x3f,%ECX

0x40b0a6 JG	40b164

0x40b0ac LEA	(%R10,%R9,4),%R9

0x40b0b0 MOV	(%R9),%R13D

0x40b0b3 LEA	-0x1(%R13),%R10D

0x40b0b7 MOV	%R10D,(%R9)

0x40b0ba TEST	%R10D,%R10D

0x40b0bd JNE	40b0d8

0x40b0bf CMP	%R8D,0xc(%R11)

0x40b0c3 JGE	40b0c7

0x40b0c5 DECL	(%RAX)

0x40b0c7 ADD	$0x8,%RSP

0x40b0cb POP	%RBX

0x40b0cc POP	%R12

0x40b0ce POP	%R13

0x40b0d0 POP	%RBP

0x40b0d1 RET

0x40b0d2 NOPW	(%RAX,%RAX,1)

0x40b0d8 MOV	0x8(%RAX),%RSI

0x40b0dc ADD	%R12D,%R10D

0x40b0df MOV	0x10(%RAX),%RCX

0x40b0e3 MOVSXD	%R10D,%R12

0x40b0e6 MOV	0x18(%RAX),%R13

0x40b0ea MOV	(%RSI,%R12,4),%EBX

0x40b0ee LEA	(%R13,%RDI,1),%R10

0x40b0f3 MOV	%EBX,(%RSI,%RDX,4)

0x40b0f6 LEA	(%R12,%R12,2),%RBX

0x40b0fa MOV	(%RCX,%R12,4),%R9D

0x40b0fe SAL	$0x3,%RBX

0x40b102 ADD	%RBX,%R13

0x40b105 MOV	%R9D,(%RCX,%RDX,4)

0x40b109 VMOVDQU	(%R13),%XMM3

0x40b10f VMOVDQU	%XMM3,(%R10)

0x40b114 MOV	0x10(%R13),%RSI

0x40b118 MOV	%RSI,0x10(%R10)

0x40b11c MOV	0x20(%RAX),%RCX

0x40b120 LEA	(%RCX,%RDI,1),%R9

0x40b124 ADD	%RBX,%RCX

0x40b127 VMOVDQU	(%RCX),%XMM4

0x40b12b VMOVDQU	%XMM4,(%R9)

0x40b130 MOV	0x10(%RCX),%R13

0x40b134 MOV	%R13,0x10(%R9)

0x40b138 MOV	0x28(%RAX),%R10

0x40b13c ADD	%R10,%RDI

0x40b13f ADD	%RBX,%R10

0x40b142 VMOVDQU	(%R10),%XMM5

0x40b147 VMOVDQU	%XMM5,(%RDI)

0x40b14b MOV	0x10(%R10),%RBX

0x40b14f MOV	%RBX,0x10(%RDI)

0x40b153 MOV	0x30(%RAX),%RDI

0x40b157 MOV	(%RDI,%R12,8),%R12

0x40b15b MOV	%R12,(%RDI,%RDX,8)

0x40b15f JMP	40b0bf

0x40b164 MOV	$0x411f00,%ECX

0x40b169 MOV	$0x106,%EDX

0x40b16e MOV	$0x411de8,%ESI

0x40b173 MOV	$0x411ea8,%EDI

0x40b178 CALL	4030c0 <__assert_fail@plt>

0x40b17d NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-272,327-335.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.50 to 6.67 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.50 to 4.17 cycles (4.68x speedup).

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 188 bytes.

General properties

nb instructions	117
nb uops	117
loop length	432
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.25	11.25	11.25	11.25	3.00	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	11.25	11.25	11.25	11.25	3.00	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.50
Dispatch	19.33
Overall L1	19.50

Vectorization ratios

all	36%
load	75%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	15%
load	20%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.50 cycles. At this rate:

16% of peak load performance is reached (15.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40afd0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %ECX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R9D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%R12D	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOVSXD %R8D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x78(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD (%RDI,%RBX,4),%ECX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA (%RDX,%RDX,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R10D,(%RSI,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV (%R13,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,(%R13,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RCX,%RCX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%R10,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM0,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x20(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R10,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM1,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x28(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R13),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM2,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R13),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x30(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%RDX,8),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R13,(%RSI,%RCX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x78(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R10,%RBX,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RSI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x1(%RBX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %ECX,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x3f,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JG 40b164 <moveAtom+0x194>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
LEA (%R10,%R9,4),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA -0x1(%R13),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10D,(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 40b0d8 <moveAtom+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP %R8D,0xc(%R11)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JGE 40b0c7 <moveAtom+0xf7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
DECL (%RAX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R12D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %R10D,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x18(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%R12,4),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R13,%RDI,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,(%RSI,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%R12,%R12,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RCX,%R12,4),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %RBX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R9D,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVDQU (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM3,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R13),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RSI,0x10(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x20(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RDI,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM4,(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%RCX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R13,0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x28(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RBX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM5,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RBX,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI,%R12,8),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R12,(%RDI,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 40b0bf <moveAtom+0xef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV $0x411f00,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x106,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x411ea8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-272,327-335.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.50 to 6.67 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 188 bytes.

General properties

nb instructions	117
nb uops	117
loop length	432
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.25	11.25	11.25	11.25	3.00	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	11.25	11.25	11.25	11.25	3.00	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.50
Dispatch	19.33
Overall L1	19.50

Vectorization ratios

all	36%
load	75%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	15%
load	20%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.50 cycles. At this rate:

16% of peak load performance is reached (15.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40afd0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %ECX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R8D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R9D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%R12D	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOVSXD %R8D,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %R12D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %EDX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x78(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RSI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD (%RDI,%RBX,4),%ECX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
LEA (%RDX,%RDX,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV %R10D,(%RSI,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV (%R13,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,(%R13,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RCX,%RCX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%R10,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM0,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x20(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R10,%RSI,1),%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM1,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x28(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RDI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R13),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM2,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R13),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10,0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x30(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%RDX,8),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R13,(%RSI,%RCX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x78(%R11),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R10,%RBX,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RSI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x1(%RBX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %ECX,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x3f,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JG 40b164 <moveAtom+0x194>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
LEA (%R10,%R9,4),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%R9),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA -0x1(%R13),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10D,(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 40b0d8 <moveAtom+0x108>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CMP %R8D,0xc(%R11)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JGE 40b0c7 <moveAtom+0xf7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
DECL (%RAX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0x8(%RAX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R12D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %R10D,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x18(%RAX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RSI,%R12,4),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%R13,%RDI,1),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,(%RSI,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%R12,%R12,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RCX,%R12,4),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %RBX,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R9D,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVDQU (%R13),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM3,(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R13),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RSI,0x10(%R10)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x20(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RDI,1),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM4,(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%RCX),%R13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R13,0x10(%R9)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x28(%RAX),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD %RBX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVDQU (%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
VMOVDQU %XMM5,(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x10(%R10),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RBX,0x10(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x30(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDI,%R12,8),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R12,(%RDI,%RDX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 40b0bf <moveAtom+0xef>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV $0x411f00,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x106,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x411ea8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.75	0	1	0	0.38	0.01	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.03	0.01
2x2	2	0.75	1.5	2	0.04	0.01
2x4	2	1	1	4	0.01	0
2x8	2	0.38	3	8	0.04	0.01
2x16	2	1	1	16	0.03	0.01
2x32	2	1	1	32	0.02	0.01
2x64	2	1	1	64	0.03	0
2x96	2	1	1	96	0.03	0

Name	Coverage (%)	Time (s)
○moveAtom	0.01	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency