OV - - Function getBoxFromTuple

	Function: getBoxFromTuple	Module: exec	Source: linkCells.c:204-250	Coverage: 0.03%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 204 - 250

--------------------------------------------------------------------------------

204: {

205:    int iBox = 0;

206:    const int* gridSize = boxes->gridSize; // alias

207:

208:    // Halo in Z+

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

248:

249:    return iBox;

250: }

0x40ad00 PUSH	%RBP

0x40ad01 MOV	%EDX,%EAX

0x40ad03 MOV	0x8(%RDI),%EDX

0x40ad06 MOV	%ECX,%R9D

0x40ad09 MOV	%ESI,%R8D

0x40ad0c MOV	(%RDI),%ECX

0x40ad0e MOV	0x4(%RDI),%ESI

0x40ad11 MOV	%RSP,%RBP

0x40ad14 CMP	%R9D,%EDX

0x40ad17 JE	40ad90

0x40ad19 CMP	$-0x1,%R9D

0x40ad1d JE	40ad58

0x40ad1f CMP	%ESI,%EAX

0x40ad21 JE	40ade0

0x40ad27 CMP	$-0x1,%EAX

0x40ad2a JE	40adc0

0x40ad30 CMP	%ECX,%R8D

0x40ad33 JE	40ae08

0x40ad39 CMP	$-0x1,%R8D

0x40ad3d JE	40ae20

0x40ad43 IMUL	%ECX,%ESI

0x40ad46 IMUL	%ECX,%EAX

0x40ad49 IMUL	%R9D,%ESI

0x40ad4d ADD	%R8D,%EAX

0x40ad50 ADD	%ESI,%EAX

0x40ad52 JMP	40ad79

0x40ad54 NOPL	(%RAX)

0x40ad58 IMUL	%EDX,%ESI

0x40ad5b ADD	$0x2,%ECX

0x40ad5e MOV	0xc(%RDI),%R9D

0x40ad62 INC	%EAX

0x40ad64 IMUL	%ECX,%EDX

0x40ad67 IMUL	%ECX,%EAX

0x40ad6a LEA	(%R9,%RSI,2),%R10D

0x40ad6e LEA	(%R10,%RDX,2),%EDX

0x40ad72 ADD	%EDX,%EAX

0x40ad74 LEA	0x1(%R8,%RAX,1),%EAX

0x40ad79 TEST	%EAX,%EAX

0x40ad7b JS	40ae2e

0x40ad81 CMP	%EAX,0x14(%RDI)

0x40ad84 JLE	40ae47

0x40ad8a POP	%RBP

0x40ad8b RET

0x40ad8c NOPL	(%RAX)

0x40ad90 MOV	%EDX,%R11D

0x40ad93 ADD	$0x2,%ECX

0x40ad96 MOV	0xc(%RDI),%R9D

0x40ad9a INC	%EAX

0x40ad9c IMUL	%ESI,%R11D

0x40ada0 ADD	$0x2,%ESI

0x40ada3 IMUL	%ECX,%EDX

0x40ada6 IMUL	%ECX,%ESI

0x40ada9 IMUL	%ECX,%EAX

0x40adac LEA	(%R9,%R11,2),%R10D

0x40adb0 LEA	(%R10,%RDX,2),%EDX

0x40adb4 ADD	%EDX,%ESI

0x40adb6 ADD	%ESI,%EAX

0x40adb8 LEA	0x1(%R8,%RAX,1),%EAX

0x40adbd JMP	40ad79

0x40adbf NOP

0x40adc0 IMUL	%ESI,%EDX

0x40adc3 ADD	$0x2,%ECX

0x40adc6 MOV	0xc(%RDI),%EAX

0x40adc9 IMUL	%R9D,%ECX

0x40adcd LEA	(%RAX,%RDX,2),%R10D

0x40add1 ADD	%ECX,%R10D

0x40add4 LEA	0x1(%R8,%R10,1),%EAX

0x40add9 JMP	40ad79

0x40addb NOPL	(%RAX,%RAX,1)

0x40ade0 IMUL	%EDX,%EAX

0x40ade3 ADD	$0x2,%ECX

0x40ade6 MOV	0xc(%RDI),%R11D

0x40adea IMUL	%ECX,%EDX

0x40aded IMUL	%R9D,%ECX

0x40adf1 LEA	(%R11,%RAX,2),%ESI

0x40adf5 ADD	%ESI,%EDX

0x40adf7 ADD	%ECX,%EDX

0x40adf9 LEA	0x1(%R8,%RDX,1),%EAX

0x40adfe JMP	40ad79

0x40ae03 NOPL	(%RAX,%RAX,1)

0x40ae08 IMUL	%ESI,%EDX

0x40ae0b ADD	0xc(%RDI),%EDX

0x40ae0e IMUL	%R9D,%ESI

0x40ae12 ADD	%ESI,%EDX

0x40ae14 ADD	%EDX,%EAX

0x40ae16 JMP	40ad79

0x40ae1b NOPL	(%RAX,%RAX,1)

0x40ae20 IMUL	%R9D,%ESI

0x40ae24 ADD	0xc(%RDI),%ESI

0x40ae27 ADD	%ESI,%EAX

0x40ae29 JMP	40ad79

0x40ae2e MOV	$0x411f10,%ECX

0x40ae33 MOV	$0xf6,%EDX

0x40ae38 MOV	$0x411de8,%ESI

0x40ae3d MOV	$0x411ec7,%EDI

0x40ae42 CALL	4030c0 <__assert_fail@plt>

0x40ae47 MOV	$0x411f10,%ECX

0x40ae4c MOV	$0xf7,%EDX

0x40ae51 MOV	$0x411de8,%ESI

0x40ae56 MOV	$0x411ed1,%EDI

0x40ae5b CALL	4030c0 <__assert_fail@plt>

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=21

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 21 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.25 to 1.14 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 2 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	101
nb uops	101
loop length	352
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.25	18.25	18.00	18.00	8.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.25	18.25	18.00	18.00	8.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	18.25
Overall L1	18.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.25 cycles. At this rate:

2% of peak load performance is reached (2.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40ad00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%RDI),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x4(%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
CMP %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ad90 <getBoxFromTuple+0x90>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ad58 <getBoxFromTuple+0x58>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ade0 <getBoxFromTuple+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40adc0 <getBoxFromTuple+0xc0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ae08 <getBoxFromTuple+0x108>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ae20 <getBoxFromTuple+0x120>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R9,%RSI,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDX,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JS 40ae2e <getBoxFromTuple+0x12e>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %EAX,0x14(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 40ae47 <getBoxFromTuple+0x147>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %EDX,%R11D	1	0	0	0	0	0	0	0	0	0	0.17
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R9,%R11,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDX,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R9D,%ECX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RAX,%RDX,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ECX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%R10,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R9D,%ECX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R11,%RAX,2),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RDX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1
ADD 0xc(%RDI),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD 0xc(%RDI),%ESI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOV $0x411f10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0xf6,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411ec7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV $0x411f10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0xf7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411ed1,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=21

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 2 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes.

General properties

nb instructions	101
nb uops	101
loop length	352
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	18.25	18.25	18.00	18.00	8.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.25	18.25	18.00	18.00	8.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	18.25
Overall L1	18.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.25 cycles. At this rate:

2% of peak load performance is reached (2.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40ad00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%RDI),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %ECX,%R9D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x4(%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
CMP %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ad90 <getBoxFromTuple+0x90>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ad58 <getBoxFromTuple+0x58>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ade0 <getBoxFromTuple+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40adc0 <getBoxFromTuple+0xc0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ae08 <getBoxFromTuple+0x108>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP $-0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 40ae20 <getBoxFromTuple+0x120>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R9,%RSI,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDX,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JS 40ae2e <getBoxFromTuple+0x12e>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMP %EAX,0x14(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 40ae47 <getBoxFromTuple+0x147>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %EDX,%R11D	1	0	0	0	0	0	0	0	0	0	0.17
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%ESI	1	0	1	0	0	0	0	0	0	3	1
IMUL %ECX,%EAX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R9,%R11,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDX,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %R9D,%ECX	1	0	1	0	0	0	0	0	0	3	1
LEA (%RAX,%RDX,2),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ECX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%R10,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	3	1
ADD $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0xc(%RDI),%R11D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R9D,%ECX	1	0	1	0	0	0	0	0	0	3	1
LEA (%R11,%RAX,2),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1(%R8,%RDX,1),%EAX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1
ADD 0xc(%RDI),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
IMUL %R9D,%ESI	1	0	1	0	0	0	0	0	0	3	1
ADD 0xc(%RDI),%ESI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JMP 40ad79 <getBoxFromTuple+0x79>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOV $0x411f10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0xf6,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411ec7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV $0x411f10,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0xf7,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411de8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411ed1,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	0.83	0.01	1.25	0	0.63	0.02	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.15	0.03
2x2	2	1	2	2	0.14	0.03
2x4	2	0.83	3.33	4	0.15	0.05
2x8	2	1.25	10	8	0.13	0.04
2x16	2	0.63	10	16	0.19	0.06
2x32	2	1	1	32	0.18	0.03
2x64	2	1	1	64	0.13	0.02
2x96	2	1	1	96	0.16	0.02

Name	Coverage (%)	Time (s)
○getBoxFromTuple	0.03	0.1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency