OV - - Function setTemperature._omp

	Function: setTemperature._omp_fn.0	Module: exec	Source: initAtoms.c:151-162	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 162

--------------------------------------------------------------------------------

151:    #pragma omp parallel for

152:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

153:    {

154:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

155:       {

156:          int iType = s->atoms->iSpecies[iOff];

157:          real_t mass = s->species[iType].mass;

158:          real_t sigma = sqrt(kB_eV * temperature/mass);

159:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 123);

160:          s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed);

161:          s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed);

162:          s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed);

0x409120 PUSH	%RBP

0x409121 MOV	%RSP,%RBP

0x409124 PUSH	%R15

0x409126 PUSH	%R14

0x409128 PUSH	%R13

0x40912a PUSH	%R12

0x40912c MOV	%RDI,%R12

0x40912f PUSH	%RBX

0x409130 SUB	$0x48,%RSP

0x409134 MOV	(%RDI),%R14

0x409137 CALL	403060 <omp_get_num_threads@plt>

0x40913c MOV	0x18(%R14),%R15

0x409140 MOV	%EAX,%EBX

0x409142 CALL	403160 <omp_get_thread_num@plt>

0x409147 MOV	%EAX,%R13D

0x40914a MOV	0xc(%R15),%EAX

0x40914e CLTD

0x40914f IDIV	%EBX

0x409151 CMP	%EDX,%R13D

0x409154 JL	4092b8

0x40915a IMUL	%EAX,%R13D

0x40915e ADD	%EDX,%R13D

0x409161 LEA	(%RAX,%R13,1),%ECX

0x409165 CMP	%ECX,%R13D

0x409168 JGE	4092a9

0x40916e MOVSXD	%R13D,%RSI

0x409171 MOV	%EAX,%R8D

0x409174 SAL	$0x6,%R13D

0x409178 MOV	0x78(%R15),%R11

0x40917c VMOVSD	0x8c44(%RIP),%XMM0

0x409184 ADD	%RSI,%R8

0x409187 MOV	%R13D,-0x5c(%RBP)

0x40918b VMULSD	0x8(%R12),%XMM0,%XMM5

0x409192 SAL	$0x2,%R8

0x409196 LEA	(,%RSI,4),%R12

0x40919e MOV	%R8,-0x68(%RBP)

0x4091a2 VMOVSD	%XMM5,-0x58(%RBP)

0x4091a7 NOPW	(%RAX,%RAX,1)

(62) 0x4091b0 MOV	(%R11,%R12,1),%R9D

(62) 0x4091b4 TEST	%R9D,%R9D

(62) 0x4091b7 JLE	409297

(62) 0x4091bd MOVSXD	-0x5c(%RBP),%R15

(62) 0x4091c1 MOV	0x20(%R14),%R9

(62) 0x4091c5 XOR	%R13D,%R13D

(62) 0x4091c8 SAL	$0x2,%R15

(62) 0x4091cc NOPL	(%RAX)

  (63) 0x4091d0 MOV	0x10(%R9),%RDI

  (63) 0x4091d4 MOV	0x8(%R9),%R11

  (63) 0x4091d8 MOV	$0x7b,%ESI

  (63) 0x4091dd INC	%R13D

  (63) 0x4091e0 VMOVSD	-0x58(%RBP),%XMM3

  (63) 0x4091e5 MOVSXD	(%RDI,%R15,1),%R10

  (63) 0x4091e9 MOV	(%R11,%R15,1),%EDI

  (63) 0x4091ed SAL	$0x4,%R10

  (63) 0x4091f1 ADD	0x28(%R14),%R10

  (63) 0x4091f5 VMOVSD	0x8(%R10),%XMM2

  (63) 0x4091fb VDIVSD	%XMM2,%XMM3,%XMM1

  (63) 0x4091ff VMOVSD	%XMM2,-0x50(%RBP)

  (63) 0x409204 VSQRTSD	%XMM1,%XMM1,%XMM4

  (63) 0x409208 VMOVSD	%XMM4,-0x48(%RBP)

  (63) 0x40920d CALL	40ef10 <mkSeed>

  (63) 0x409212 VMOVSD	-0x50(%RBP),%XMM6

  (63) 0x409217 VMULSD	-0x48(%RBP),%XMM6,%XMM7

  (63) 0x40921c LEA	-0x38(%RBP),%RDI

  (63) 0x409220 MOV	%RAX,-0x38(%RBP)

  (63) 0x409224 VMOVSD	%XMM7,-0x48(%RBP)

  (63) 0x409229 CALL	40edd0 <gasdev>

  (63) 0x40922e VMULSD	-0x48(%RBP),%XMM0,%XMM8

  (63) 0x409233 MOV	0x20(%R14),%RDX

  (63) 0x409237 LEA	(%R15,%R15,2),%RAX

  (63) 0x40923b LEA	-0x38(%RBP),%RDI

  (63) 0x40923f LEA	(%RAX,%RAX,1),%RBX

  (63) 0x409243 ADD	$0x4,%R15

  (63) 0x409247 MOV	0x20(%RDX),%RCX

  (63) 0x40924b VMOVSD	%XMM8,(%RCX,%RAX,2)

  (63) 0x409250 CALL	40edd0 <gasdev>

  (63) 0x409255 VMULSD	-0x48(%RBP),%XMM0,%XMM9

  (63) 0x40925a MOV	0x20(%R14),%RSI

  (63) 0x40925e LEA	-0x38(%RBP),%RDI

  (63) 0x409262 MOV	0x20(%RSI),%R8

  (63) 0x409266 VMOVSD	%XMM9,0x8(%R8,%RBX,1)

  (63) 0x40926d CALL	40edd0 <gasdev>

  (63) 0x409272 VMULSD	-0x48(%RBP),%XMM0,%XMM10

  (63) 0x409277 MOV	0x20(%R14),%R9

  (63) 0x40927b MOV	0x18(%R14),%R10

  (63) 0x40927f MOV	0x20(%R9),%RDI

  (63) 0x409283 MOV	0x78(%R10),%R11

  (63) 0x409287 VMOVSD	%XMM10,0x10(%RDI,%RBX,1)

  (63) 0x40928d CMP	%R13D,(%R11,%R12,1)

  (63) 0x409291 JG	4091d0

(62) 0x409297 ADDL	$0x40,-0x5c(%RBP)

(62) 0x40929b ADD	$0x4,%R12

(62) 0x40929f CMP	%R12,-0x68(%RBP)

(62) 0x4092a3 JNE	4091b0

0x4092a9 ADD	$0x48,%RSP

0x4092ad POP	%RBX

0x4092ae POP	%R12

0x4092b0 POP	%R13

0x4092b2 POP	%R14

0x4092b4 POP	%R15

0x4092b6 POP	%RBP

0x4092b7 RET

0x4092b8 INC	%EAX

0x4092ba XOR	%EDX,%EDX

0x4092bc JMP	40915a

0x4092c1 NOPW	%CS:(%RAX,%RAX,1)

0x4092cc NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 1.33 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.33 to 0.75 cycles (11.11x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 44 bytes (5 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	183
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.25	4.25	4.25	4.25	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.50	0.50
cycles	4.25	4.25	4.25	4.25	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	8.33
Dispatch	4.25
DIV/SQRT	6.00
Overall L1	8.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.33 cycles. At this rate:

5% of peak load performance is reached (5.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 409120

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDI),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x18(%R14),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%R15),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 4092b8 <setTemperature._omp_fn.0+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%R13D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EDX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R13,1),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %ECX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 4092a9 <setTemperature._omp_fn.0+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R13D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R13D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%R15),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x8c44(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R13D,-0x5c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMULSD 0x8(%R12),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
SAL $0x2,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (,%RSI,4),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40915a <setTemperature._omp_fn.0+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 1.33 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 44 bytes (5 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	50
loop length	183
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.25	4.25	4.25	4.25	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.50	0.50
cycles	4.25	4.25	4.25	4.25	4.00	3.67	3.67	3.67	0.50	0.50	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	8.33
Dispatch	4.25
DIV/SQRT	6.00
Overall L1	8.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.33 cycles. At this rate:

5% of peak load performance is reached (5.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 409120

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDI),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x18(%R14),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%R15),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 4092b8 <setTemperature._omp_fn.0+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%R13D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EDX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%R13,1),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %ECX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 4092a9 <setTemperature._omp_fn.0+0x189>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD %R13D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R13D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%R15),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x8c44(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD %RSI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R13D,-0x5c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMULSD 0x8(%R12),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
SAL $0x2,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (,%RSI,4),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
VMOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40915a <setTemperature._omp_fn.0+0x3a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.01
2x2	4	1	2	2	0.01	0
2x4	8	1	1	4	0	0
2x8	10	1	1	8	0	0
2x16	20	1	1	16	0	0
2x32	23	1	1	32	0	0
2x64	23	1	1	64	0	0
2x96	22	1	1	96	0	0

Name	Coverage (%)	Time (s)
▼setTemperature._omp_fn.0–	0.01	0.02
▼Loop 62 - initAtoms.c:154-162 - exec–	0	0
○Loop 63 - initAtoms.c:154-162 - exec	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency