OV - - Function setTemperature._omp

	Function: setTemperature._omp_fn.1	Module: exec	Source: initAtoms.c:174-181	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 174 - 181

--------------------------------------------------------------------------------

174:    #pragma omp parallel for

175:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

176:    {

177:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

178:       {

179:          s->atoms->p[iOff][0] *= scaleFactor;

180:          s->atoms->p[iOff][1] *= scaleFactor;

181:          s->atoms->p[iOff][2] *= scaleFactor;

0x408f60 PUSH	%RBP

0x408f61 MOV	%RSP,%RBP

0x408f64 PUSH	%R14

0x408f66 PUSH	%R13

0x408f68 MOV	%RDI,%R13

0x408f6b PUSH	%R12

0x408f6d PUSH	%RBX

0x408f6e MOV	(%RDI),%RBX

0x408f71 MOV	0x18(%RBX),%R14

0x408f75 CALL	403060 <omp_get_num_threads@plt>

0x408f7a MOV	%EAX,%R12D

0x408f7d CALL	403160 <omp_get_thread_num@plt>

0x408f82 MOV	%EAX,%ESI

0x408f84 MOV	0xc(%R14),%EAX

0x408f88 CLTD

0x408f89 IDIV	%R12D

0x408f8c CMP	%EDX,%ESI

0x408f8e JL	409116

0x408f94 IMUL	%EAX,%ESI

0x408f97 ADD	%EDX,%ESI

0x408f99 ADD	%ESI,%EAX

0x408f9b CMP	%EAX,%ESI

0x408f9d JGE	40910d

0x408fa3 VMOVSD	0x8(%R13),%XMM0

0x408fa9 MOVSXD	%ESI,%R13

0x408fac MOV	0x78(%R14),%R8

0x408fb0 LEA	(%R13,%R13,2),%RDI

0x408fb5 SAL	$0x9,%RDI

0x408fb9 NOPL	(%RAX)

(60) 0x408fc0 MOVSXD	(%R8,%R13,4),%RCX

(60) 0x408fc4 TEST	%ECX,%ECX

(60) 0x408fc6 JLE	4090fa

(60) 0x408fcc LEA	(%RCX,%RCX,2),%R10

(60) 0x408fd0 MOV	0x20(%RBX),%R9

(60) 0x408fd4 MOV	$0xaaaaaaaaaaaaaab,%R12

(60) 0x408fde LEA	-0x18(,%R10,8),%R14

(60) 0x408fe6 SHR	$0x3,%R14

(60) 0x408fea MOV	0x20(%R9),%RDX

(60) 0x408fee IMUL	%R12,%R14

(60) 0x408ff2 ADD	%RDI,%RDX

(60) 0x408ff5 LEA	(%RDX,%R10,8),%R11

(60) 0x408ff9 INC	%R14

(60) 0x408ffc AND	$0x3,%R14D

(60) 0x409000 JE	40907a

(60) 0x409002 CMP	$0x1,%R14

(60) 0x409006 JE	409050

(60) 0x409008 CMP	$0x2,%R14

(60) 0x40900c JE	40902f

(60) 0x40900e VMULSD	(%RDX),%XMM0,%XMM1

(60) 0x409012 ADD	$0x18,%RDX

(60) 0x409016 VMULSD	-0x10(%RDX),%XMM0,%XMM2

(60) 0x40901b VMULSD	-0x8(%RDX),%XMM0,%XMM3

(60) 0x409020 VMOVSD	%XMM1,-0x18(%RDX)

(60) 0x409025 VMOVSD	%XMM2,-0x10(%RDX)

(60) 0x40902a VMOVSD	%XMM3,-0x8(%RDX)

(60) 0x40902f VMULSD	(%RDX),%XMM0,%XMM4

(60) 0x409033 ADD	$0x18,%RDX

(60) 0x409037 VMULSD	-0x10(%RDX),%XMM0,%XMM5

(60) 0x40903c VMULSD	-0x8(%RDX),%XMM0,%XMM6

(60) 0x409041 VMOVSD	%XMM4,-0x18(%RDX)

(60) 0x409046 VMOVSD	%XMM5,-0x10(%RDX)

(60) 0x40904b VMOVSD	%XMM6,-0x8(%RDX)

(60) 0x409050 VMULSD	(%RDX),%XMM0,%XMM7

(60) 0x409054 ADD	$0x18,%RDX

(60) 0x409058 VMULSD	-0x10(%RDX),%XMM0,%XMM8

(60) 0x40905d VMULSD	-0x8(%RDX),%XMM0,%XMM9

(60) 0x409062 VMOVSD	%XMM7,-0x18(%RDX)

(60) 0x409067 VMOVSD	%XMM8,-0x10(%RDX)

(60) 0x40906c VMOVSD	%XMM9,-0x8(%RDX)

(60) 0x409071 CMP	%RDX,%R11

(60) 0x409074 JE	4090fa

  (61) 0x40907a VMULSD	(%RDX),%XMM0,%XMM10

  (61) 0x40907e ADD	$0x60,%RDX

  (61) 0x409082 VMULSD	-0x58(%RDX),%XMM0,%XMM11

  (61) 0x409087 VMULSD	-0x50(%RDX),%XMM0,%XMM12

  (61) 0x40908c VMULSD	-0x48(%RDX),%XMM0,%XMM13

  (61) 0x409091 VMULSD	-0x40(%RDX),%XMM0,%XMM14

  (61) 0x409096 VMULSD	-0x38(%RDX),%XMM0,%XMM15

  (61) 0x40909b VMOVSD	%XMM10,-0x60(%RDX)

  (61) 0x4090a0 VMULSD	-0x30(%RDX),%XMM0,%XMM1

  (61) 0x4090a5 VMOVSD	%XMM11,-0x58(%RDX)

  (61) 0x4090aa VMULSD	-0x28(%RDX),%XMM0,%XMM2

  (61) 0x4090af VMOVSD	%XMM12,-0x50(%RDX)

  (61) 0x4090b4 VMULSD	-0x20(%RDX),%XMM0,%XMM3

  (61) 0x4090b9 VMOVSD	%XMM13,-0x48(%RDX)

  (61) 0x4090be VMULSD	-0x18(%RDX),%XMM0,%XMM4

  (61) 0x4090c3 VMOVSD	%XMM14,-0x40(%RDX)

  (61) 0x4090c8 VMULSD	-0x10(%RDX),%XMM0,%XMM5

  (61) 0x4090cd VMOVSD	%XMM15,-0x38(%RDX)

  (61) 0x4090d2 VMULSD	-0x8(%RDX),%XMM0,%XMM6

  (61) 0x4090d7 VMOVSD	%XMM1,-0x30(%RDX)

  (61) 0x4090dc VMOVSD	%XMM2,-0x28(%RDX)

  (61) 0x4090e1 VMOVSD	%XMM3,-0x20(%RDX)

  (61) 0x4090e6 VMOVSD	%XMM4,-0x18(%RDX)

  (61) 0x4090eb VMOVSD	%XMM5,-0x10(%RDX)

  (61) 0x4090f0 VMOVSD	%XMM6,-0x8(%RDX)

  (61) 0x4090f5 CMP	%RDX,%R11

  (61) 0x4090f8 JNE	40907a

(60) 0x4090fa INC	%R13

(60) 0x4090fd ADD	$0x600,%RDI

(60) 0x409104 CMP	%R13D,%EAX

(60) 0x409107 JG	408fc0

0x40910d POP	%RBX

0x40910e POP	%R12

0x409110 POP	%R13

0x409112 POP	%R14

0x409114 POP	%RBP

0x409115 RET

0x409116 INC	%EAX

0x409118 XOR	%EDX,%EDX

0x40911a JMP	408f94

0x40911f NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initAtoms.c:174-181
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:174-181.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.50 to 0.75 cycles (8.67x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes.

General properties

nb instructions	39
nb uops	39
loop length	115
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	3.00	3.00	3.00	4.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	3.00	3.00	3.00	4.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.50
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

5% of peak load performance is reached (5.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 408f60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV (%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %R12D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 409116 <setTemperature._omp_fn.1+0x1b6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40910d <setTemperature._omp_fn.1+0x1ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x8(%R13),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD %ESI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x78(%R14),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R13,%R13,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x9,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 408f94 <setTemperature._omp_fn.1+0x34>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	initAtoms.c:174-181
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:174-181.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes.

General properties

nb instructions	39
nb uops	39
loop length	115
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	3.00	3.00	3.00	4.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	3.00	3.00	3.00	4.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.50
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

5% of peak load performance is reached (5.54 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 408f60

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV (%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RBX),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %R12D	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 409116 <setTemperature._omp_fn.1+0x1b6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EDX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40910d <setTemperature._omp_fn.1+0x1ad>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x8(%R13),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSXD %ESI,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x78(%R14),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R13,%R13,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SAL $0x9,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 408f94 <setTemperature._omp_fn.1+0x34>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.01
2x2	4	1	2	2	0	0
2x4	8	1	1	4	0	0
2x8	16	1	1	8	0	0
2x16	1	1	1	16	0	0
2x32	9	1	1	32	0	0.01
2x64	11	1	1	64	0	0
2x96	1	1	1	96	0	0

Name	Coverage (%)	Time (s)
▼setTemperature._omp_fn.1–	0.01	0.02
▼Loop 60 - initAtoms.c:177-181 - exec–	0	0
○Loop 61 - initAtoms.c:177-181 - exec	0.01	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency