OV - - Loop 96

	Loop Id: 96	Module: exec	Source: timestep.c:74-78	Coverage: 0.51%

0x40f418 MOVSXD	(%R9,%R12,4),%RDI

0x40f41c TEST	%EDI,%EDI

0x40f41e JLE	40f7f2

0x40f424 MOV	0x20(%R10),%R11

0x40f428 LEA	(%RDI,%RDI,2),%RBX

0x40f42c LEA	-0x18(,%RBX,8),%RDI

0x40f434 MOV	0x20(%R11),%RSI

0x40f438 MOV	0x28(%R11),%RCX

0x40f43c SHR	$0x3,%RDI

0x40f440 MOV	$0xaaaaaaaaaaaaaab,%R11

0x40f44a IMUL	%R11,%RDI

0x40f44e ADD	%R8,%RSI

0x40f451 ADD	%R8,%RCX

0x40f454 LEA	(%RSI,%RBX,8),%RDX

0x40f458 INC	%RDI

0x40f45b AND	$0x7,%EDI

0x40f45e JE	40f61b

0x40f464 CMP	$0x1,%RDI

0x40f468 JE	40f5dc

0x40f46e CMP	$0x2,%RDI

0x40f472 JE	40f5a6

0x40f478 CMP	$0x3,%RDI

0x40f47c JE	40f570

0x40f482 CMP	$0x4,%RDI

0x40f486 JE	40f53a

0x40f48c CMP	$0x5,%RDI

0x40f490 JE	40f504

0x40f492 CMP	$0x6,%RDI

0x40f496 JE	40f4ce

0x40f498 VMOVSD	(%RCX),%XMM1

0x40f49c VFMADD213SD	(%RSI),%XMM0,%XMM1

0x40f4a1 ADD	$0x18,%RCX

0x40f4a5 ADD	$0x18,%RSI

0x40f4a9 VMOVSD	%XMM1,-0x18(%RSI)

0x40f4ae VMOVSD	-0x10(%RCX),%XMM2

0x40f4b3 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM2

0x40f4b9 VMOVSD	%XMM2,-0x10(%RSI)

0x40f4be VMOVSD	-0x8(%RCX),%XMM3

0x40f4c3 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM3

0x40f4c9 VMOVSD	%XMM3,-0x8(%RSI)

0x40f4ce VMOVSD	(%RCX),%XMM4

0x40f4d2 VFMADD213SD	(%RSI),%XMM0,%XMM4

0x40f4d7 ADD	$0x18,%RCX

0x40f4db ADD	$0x18,%RSI

0x40f4df VMOVSD	%XMM4,-0x18(%RSI)

0x40f4e4 VMOVSD	-0x10(%RCX),%XMM5

0x40f4e9 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM5

0x40f4ef VMOVSD	%XMM5,-0x10(%RSI)

0x40f4f4 VMOVSD	-0x8(%RCX),%XMM6

0x40f4f9 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM6

0x40f4ff VMOVSD	%XMM6,-0x8(%RSI)

0x40f504 VMOVSD	(%RCX),%XMM7

0x40f508 VFMADD213SD	(%RSI),%XMM0,%XMM7

0x40f50d ADD	$0x18,%RCX

0x40f511 ADD	$0x18,%RSI

0x40f515 VMOVSD	%XMM7,-0x18(%RSI)

0x40f51a VMOVSD	-0x10(%RCX),%XMM8

0x40f51f VFMADD213SD	-0x10(%RSI),%XMM0,%XMM8

0x40f525 VMOVSD	%XMM8,-0x10(%RSI)

0x40f52a VMOVSD	-0x8(%RCX),%XMM9

0x40f52f VFMADD213SD	-0x8(%RSI),%XMM0,%XMM9

0x40f535 VMOVSD	%XMM9,-0x8(%RSI)

0x40f53a VMOVSD	(%RCX),%XMM10

0x40f53e VFMADD213SD	(%RSI),%XMM0,%XMM10

0x40f543 ADD	$0x18,%RCX

0x40f547 ADD	$0x18,%RSI

0x40f54b VMOVSD	%XMM10,-0x18(%RSI)

0x40f550 VMOVSD	-0x10(%RCX),%XMM11

0x40f555 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM11

0x40f55b VMOVSD	%XMM11,-0x10(%RSI)

0x40f560 VMOVSD	-0x8(%RCX),%XMM12

0x40f565 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM12

0x40f56b VMOVSD	%XMM12,-0x8(%RSI)

0x40f570 VMOVSD	(%RCX),%XMM13

0x40f574 VFMADD213SD	(%RSI),%XMM0,%XMM13

0x40f579 ADD	$0x18,%RCX

0x40f57d ADD	$0x18,%RSI

0x40f581 VMOVSD	%XMM13,-0x18(%RSI)

0x40f586 VMOVSD	-0x10(%RCX),%XMM14

0x40f58b VFMADD213SD	-0x10(%RSI),%XMM0,%XMM14

0x40f591 VMOVSD	%XMM14,-0x10(%RSI)

0x40f596 VMOVSD	-0x8(%RCX),%XMM15

0x40f59b VFMADD213SD	-0x8(%RSI),%XMM0,%XMM15

0x40f5a1 VMOVSD	%XMM15,-0x8(%RSI)

0x40f5a6 VMOVSD	(%RCX),%XMM1

0x40f5aa VFMADD213SD	(%RSI),%XMM0,%XMM1

0x40f5af ADD	$0x18,%RCX

0x40f5b3 ADD	$0x18,%RSI

0x40f5b7 VMOVSD	%XMM1,-0x18(%RSI)

0x40f5bc VMOVSD	-0x10(%RCX),%XMM2

0x40f5c1 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM2

0x40f5c7 VMOVSD	%XMM2,-0x10(%RSI)

0x40f5cc VMOVSD	-0x8(%RCX),%XMM3

0x40f5d1 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM3

0x40f5d7 VMOVSD	%XMM3,-0x8(%RSI)

0x40f5dc VMOVSD	(%RCX),%XMM4

0x40f5e0 VFMADD213SD	(%RSI),%XMM0,%XMM4

0x40f5e5 ADD	$0x18,%RSI

0x40f5e9 ADD	$0x18,%RCX

0x40f5ed VMOVSD	%XMM4,-0x18(%RSI)

0x40f5f2 VMOVSD	-0x10(%RCX),%XMM5

0x40f5f7 VFMADD213SD	-0x10(%RSI),%XMM0,%XMM5

0x40f5fd VMOVSD	%XMM5,-0x10(%RSI)

0x40f602 VMOVSD	-0x8(%RCX),%XMM6

0x40f607 VFMADD213SD	-0x8(%RSI),%XMM0,%XMM6

0x40f60d VMOVSD	%XMM6,-0x8(%RSI)

0x40f612 CMP	%RSI,%RDX

0x40f615 JE	40f7f2

  (97) 0x40f61b VMOVSD	(%RCX),%XMM7

  (97) 0x40f61f VFMADD213SD	(%RSI),%XMM0,%XMM7

  (97) 0x40f624 ADD	$0xc0,%RSI

  (97) 0x40f62b ADD	$0xc0,%RCX

  (97) 0x40f632 VMOVSD	%XMM7,-0xc0(%RSI)

  (97) 0x40f63a VMOVSD	-0xb8(%RCX),%XMM8

  (97) 0x40f642 VFMADD213SD	-0xb8(%RSI),%XMM0,%XMM8

  (97) 0x40f64b VMOVSD	%XMM8,-0xb8(%RSI)

  (97) 0x40f653 VMOVSD	-0xb0(%RCX),%XMM9

  (97) 0x40f65b VFMADD213SD	-0xb0(%RSI),%XMM0,%XMM9

  (97) 0x40f664 VMOVSD	%XMM9,-0xb0(%RSI)

  (97) 0x40f66c VMOVSD	-0xa8(%RCX),%XMM10

  (97) 0x40f674 VFMADD213SD	-0xa8(%RSI),%XMM0,%XMM10

  (97) 0x40f67d VMOVSD	%XMM10,-0xa8(%RSI)

  (97) 0x40f685 VMOVSD	-0xa0(%RCX),%XMM11

  (97) 0x40f68d VFMADD213SD	-0xa0(%RSI),%XMM0,%XMM11

  (97) 0x40f696 VMOVSD	%XMM11,-0xa0(%RSI)

  (97) 0x40f69e VMOVSD	-0x98(%RCX),%XMM12

  (97) 0x40f6a6 VFMADD213SD	-0x98(%RSI),%XMM0,%XMM12

  (97) 0x40f6af VMOVSD	%XMM12,-0x98(%RSI)

  (97) 0x40f6b7 VMOVSD	-0x90(%RCX),%XMM13

  (97) 0x40f6bf VFMADD213SD	-0x90(%RSI),%XMM0,%XMM13

  (97) 0x40f6c8 VMOVSD	%XMM13,-0x90(%RSI)

  (97) 0x40f6d0 VMOVSD	-0x88(%RCX),%XMM14

  (97) 0x40f6d8 VFMADD213SD	-0x88(%RSI),%XMM0,%XMM14

  (97) 0x40f6e1 VMOVSD	%XMM14,-0x88(%RSI)

  (97) 0x40f6e9 VMOVSD	-0x80(%RCX),%XMM15

  (97) 0x40f6ee VFMADD213SD	-0x80(%RSI),%XMM0,%XMM15

  (97) 0x40f6f4 VMOVSD	%XMM15,-0x80(%RSI)

  (97) 0x40f6f9 VMOVSD	-0x78(%RCX),%XMM1

  (97) 0x40f6fe VFMADD213SD	-0x78(%RSI),%XMM0,%XMM1

  (97) 0x40f704 VMOVSD	%XMM1,-0x78(%RSI)

  (97) 0x40f709 VMOVSD	-0x70(%RCX),%XMM2

  (97) 0x40f70e VFMADD213SD	-0x70(%RSI),%XMM0,%XMM2

  (97) 0x40f714 VMOVSD	%XMM2,-0x70(%RSI)

  (97) 0x40f719 VMOVSD	-0x68(%RCX),%XMM3

  (97) 0x40f71e VFMADD213SD	-0x68(%RSI),%XMM0,%XMM3

  (97) 0x40f724 VMOVSD	%XMM3,-0x68(%RSI)

  (97) 0x40f729 VMOVSD	-0x60(%RCX),%XMM4

  (97) 0x40f72e VFMADD213SD	-0x60(%RSI),%XMM0,%XMM4

  (97) 0x40f734 VMOVSD	%XMM4,-0x60(%RSI)

  (97) 0x40f739 VMOVSD	-0x58(%RCX),%XMM5

  (97) 0x40f73e VFMADD213SD	-0x58(%RSI),%XMM0,%XMM5

  (97) 0x40f744 VMOVSD	%XMM5,-0x58(%RSI)

  (97) 0x40f749 VMOVSD	-0x50(%RCX),%XMM6

  (97) 0x40f74e VFMADD213SD	-0x50(%RSI),%XMM0,%XMM6

  (97) 0x40f754 VMOVSD	%XMM6,-0x50(%RSI)

  (97) 0x40f759 VMOVSD	-0x48(%RCX),%XMM7

  (97) 0x40f75e VFMADD213SD	-0x48(%RSI),%XMM0,%XMM7

  (97) 0x40f764 VMOVSD	%XMM7,-0x48(%RSI)

  (97) 0x40f769 VMOVSD	-0x40(%RCX),%XMM8

  (97) 0x40f76e VFMADD213SD	-0x40(%RSI),%XMM0,%XMM8

  (97) 0x40f774 VMOVSD	%XMM8,-0x40(%RSI)

  (97) 0x40f779 VMOVSD	-0x38(%RCX),%XMM9

  (97) 0x40f77e VFMADD213SD	-0x38(%RSI),%XMM0,%XMM9

  (97) 0x40f784 VMOVSD	%XMM9,-0x38(%RSI)

  (97) 0x40f789 VMOVSD	-0x30(%RCX),%XMM10

  (97) 0x40f78e VFMADD213SD	-0x30(%RSI),%XMM0,%XMM10

  (97) 0x40f794 VMOVSD	%XMM10,-0x30(%RSI)

  (97) 0x40f799 VMOVSD	-0x28(%RCX),%XMM11

  (97) 0x40f79e VFMADD213SD	-0x28(%RSI),%XMM0,%XMM11

  (97) 0x40f7a4 VMOVSD	%XMM11,-0x28(%RSI)

  (97) 0x40f7a9 VMOVSD	-0x20(%RCX),%XMM12

  (97) 0x40f7ae VFMADD213SD	-0x20(%RSI),%XMM0,%XMM12

  (97) 0x40f7b4 VMOVSD	%XMM12,-0x20(%RSI)

  (97) 0x40f7b9 VMOVSD	-0x18(%RCX),%XMM13

  (97) 0x40f7be VFMADD213SD	-0x18(%RSI),%XMM0,%XMM13

  (97) 0x40f7c4 VMOVSD	%XMM13,-0x18(%RSI)

  (97) 0x40f7c9 VMOVSD	-0x10(%RCX),%XMM14

  (97) 0x40f7ce VFMADD213SD	-0x10(%RSI),%XMM0,%XMM14

  (97) 0x40f7d4 VMOVSD	%XMM14,-0x10(%RSI)

  (97) 0x40f7d9 VMOVSD	-0x8(%RCX),%XMM15

  (97) 0x40f7de VFMADD213SD	-0x8(%RSI),%XMM0,%XMM15

  (97) 0x40f7e4 VMOVSD	%XMM15,-0x8(%RSI)

  (97) 0x40f7e9 CMP	%RSI,%RDX

  (97) 0x40f7ec JNE	40f61b

0x40f7f2 INC	%R12

0x40f7f5 ADD	$0x600,%R8

0x40f7fc CMP	%R12D,%EAX

0x40f7ff JG	40f418

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	4.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P5, P6, P7,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.33
CQA cycles if no scalar integer	21.33
CQA cycles if FP arith vectorized	21.33
CQA cycles if fully vectorized	4.71
Front-end cycles	18.50
DIV/SQRT cycles	10.00
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	5.00
P4 cycles	22.33
P5 cycles	22.33
P6 cycles	22.33
P7 cycles	10.50
P8 cycles	10.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	111.00
Nb loads	46.00
Nb stores	21.00
Nb stack references	0.00
FLOP/cycle	1.88
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.82
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.41
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	4.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P5, P6, P7,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.33
CQA cycles if no scalar integer	21.33
CQA cycles if FP arith vectorized	21.33
CQA cycles if fully vectorized	4.71
Front-end cycles	18.50
DIV/SQRT cycles	10.00
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	5.00
P4 cycles	22.33
P5 cycles	22.33
P6 cycles	22.33
P7 cycles	10.50
P8 cycles	10.50
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	112.00
Nb uops	111.00
Nb loads	46.00
Nb stores	21.00
Nb stack references	0.00
FLOP/cycle	1.88
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.82
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.41
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 22.33 to 4.71 cycles (4.74x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 22.33 to 18.50 cycles (1.21x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 21 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes (45 double precision FP elements). The binary loop is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	111
loop length	534
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.00	10.00	10.00	10.00	5.00	22.33	22.33	22.33	10.50	10.50	0.00	0.00	10.50	10.50
cycles	10.00	10.00	10.00	10.00	5.00	22.33	22.33	22.33	10.50	10.50	0.00	0.00	10.50	10.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.50
Dispatch	22.33
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.33 cycles. At this rate:

16% of peak load performance is reached (16.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.52 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f418

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVSXD (%R9,%R12,4),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
TEST %EDI,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 40f7f2 <advanceVelocity._omp_fn.0+0x432>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x20(%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA (%RDI,%RDI,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x18(,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%R11),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SHR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0xaaaaaaaaaaaaaab,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33
IMUL %R11,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RBX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f61b <advanceVelocity._omp_fn.0+0x25b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f5dc <advanceVelocity._omp_fn.0+0x21c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f5a6 <advanceVelocity._omp_fn.0+0x1e6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f570 <advanceVelocity._omp_fn.0+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f53a <advanceVelocity._omp_fn.0+0x17a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f504 <advanceVelocity._omp_fn.0+0x144>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f4ce <advanceVelocity._omp_fn.0+0x10e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM7,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f7f2 <advanceVelocity._omp_fn.0+0x432>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x600,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JG 40f418 <advanceVelocity._omp_fn.0+0x58>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 22.33 to 18.50 cycles (1.21x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 21 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes (45 double precision FP elements). The binary loop is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	112
nb uops	111
loop length	534
used x86 registers	11
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.00	10.00	10.00	10.00	5.00	22.33	22.33	22.33	10.50	10.50	0.00	0.00	10.50	10.50
cycles	10.00	10.00	10.00	10.00	5.00	22.33	22.33	22.33	10.50	10.50	0.00	0.00	10.50	10.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.50
Dispatch	22.33
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.33 cycles. At this rate:

16% of peak load performance is reached (16.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.52 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f418

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVSXD (%R9,%R12,4),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
TEST %EDI,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JLE 40f7f2 <advanceVelocity._omp_fn.0+0x432>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV 0x20(%R10),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
LEA (%RDI,%RDI,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x18(,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%R11),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x28(%R11),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
SHR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOV $0xaaaaaaaaaaaaaab,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.33
IMUL %R11,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %R8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RBX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f61b <advanceVelocity._omp_fn.0+0x25b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f5dc <advanceVelocity._omp_fn.0+0x21c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f5a6 <advanceVelocity._omp_fn.0+0x1e6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f570 <advanceVelocity._omp_fn.0+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f53a <advanceVelocity._omp_fn.0+0x17a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f504 <advanceVelocity._omp_fn.0+0x144>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f4ce <advanceVelocity._omp_fn.0+0x10e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM7,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM1,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD (%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JE 40f7f2 <advanceVelocity._omp_fn.0+0x432>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x600,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JG 40f418 <advanceVelocity._omp_fn.0+0x58>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.04	0	0.98	0.01	1.01	-0	0.88	0.05	0.65	0.16	0.45	0.24	0.15	0.86

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	1.57	0.51
2x2	4	1.04	2.07	2	0.8	0.47
2x4	8	0.98	3.92	4	0.44	0.48
2x8	16	1.01	8.06	8	0.2	0.42
2x16	32	0.88	14.5	16.5	0.16	0.39
2x32	64	0.65	20.71	32	0.08	0.46
2x64	128	0.45	29	64	0.07	0.43
2x96	192	0.15	14.5	96	0.12	1.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency