OV - - Loop 95

	Loop Id: 95	Module: exec	Source: timestep.c:88-94	Coverage: 0.52%

0x40f27e MOVSXD	(%RSI),%R8    [4]

0x40f281 VMULSD	(%RCX),%XMM0,%XMM15    [8]

0x40f285 ADD	$0x10,%RSI

0x40f289 ADD	$0x60,%RDX

0x40f28d MOVSXD	-0xc(%RSI),%R14    [7]

0x40f291 ADD	$0x60,%RCX

0x40f295 SAL	$0x4,%R8

0x40f299 VDIVSD	0x8(%RDI,%R8,1),%XMM2,%XMM14    [1]

0x40f2a0 SAL	$0x4,%R14

0x40f2a4 MOVSXD	-0x8(%RSI),%R8    [7]

0x40f2a8 VFMADD213SD	-0x60(%RDX),%XMM14,%XMM15    [6]

0x40f2ae SAL	$0x4,%R8

0x40f2b2 VMOVSD	%XMM15,-0x60(%RDX)    [6]

0x40f2b7 VMULSD	-0x58(%RCX),%XMM0,%XMM1    [3]

0x40f2bc VFMADD213SD	-0x58(%RDX),%XMM14,%XMM1    [6]

0x40f2c2 VMOVSD	%XMM1,-0x58(%RDX)    [6]

0x40f2c7 VMULSD	-0x50(%RCX),%XMM0,%XMM3    [3]

0x40f2cc VFMADD213SD	-0x50(%RDX),%XMM3,%XMM14    [6]

0x40f2d2 VMOVSD	%XMM14,-0x50(%RDX)    [6]

0x40f2d7 VMULSD	-0x48(%RCX),%XMM0,%XMM5    [3]

0x40f2dc VDIVSD	0x8(%RDI,%R14,1),%XMM2,%XMM4    [9]

0x40f2e3 VFMADD213SD	-0x48(%RDX),%XMM4,%XMM5    [6]

0x40f2e9 VMOVSD	%XMM5,-0x48(%RDX)    [6]

0x40f2ee VMULSD	-0x40(%RCX),%XMM0,%XMM6    [3]

0x40f2f3 VFMADD213SD	-0x40(%RDX),%XMM4,%XMM6    [6]

0x40f2f9 VMOVSD	%XMM6,-0x40(%RDX)    [6]

0x40f2fe VMULSD	-0x38(%RCX),%XMM0,%XMM7    [3]

0x40f303 VFMADD213SD	-0x38(%RDX),%XMM7,%XMM4    [6]

0x40f309 VMOVSD	%XMM4,-0x38(%RDX)    [6]

0x40f30e VMULSD	-0x30(%RCX),%XMM0,%XMM9    [3]

0x40f313 VDIVSD	0x8(%RDI,%R8,1),%XMM2,%XMM8    [5]

0x40f31a VFMADD213SD	-0x30(%RDX),%XMM8,%XMM9    [6]

0x40f320 VMOVSD	%XMM9,-0x30(%RDX)    [6]

0x40f325 VMULSD	-0x28(%RCX),%XMM0,%XMM10    [3]

0x40f32a VFMADD213SD	-0x28(%RDX),%XMM8,%XMM10    [6]

0x40f330 VMOVSD	%XMM10,-0x28(%RDX)    [6]

0x40f335 VMULSD	-0x20(%RCX),%XMM0,%XMM11    [3]

0x40f33a VFMADD213SD	-0x20(%RDX),%XMM11,%XMM8    [6]

0x40f340 VMOVSD	%XMM8,-0x20(%RDX)    [6]

0x40f345 MOVSXD	-0x4(%RSI),%R14    [7]

0x40f349 VMULSD	-0x18(%RCX),%XMM0,%XMM13    [3]

0x40f34e SAL	$0x4,%R14

0x40f352 VDIVSD	0x8(%RDI,%R14,1),%XMM2,%XMM12    [2]

0x40f359 VFMADD213SD	-0x18(%RDX),%XMM12,%XMM13    [6]

0x40f35f VMOVSD	%XMM13,-0x18(%RDX)    [6]

0x40f364 VMULSD	-0x10(%RCX),%XMM0,%XMM14    [3]

0x40f369 VFMADD213SD	-0x10(%RDX),%XMM12,%XMM14    [6]

0x40f36f VMOVSD	%XMM14,-0x10(%RDX)    [6]

0x40f374 VMULSD	-0x8(%RCX),%XMM0,%XMM15    [3]

0x40f379 VFMADD213SD	-0x8(%RDX),%XMM15,%XMM12    [6]

0x40f37f VMOVSD	%XMM12,-0x8(%RDX)    [6]

0x40f384 CMP	%RSI,%R11

0x40f387 JNE	40f27e

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	P8, P9,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	5.00
Front-end cycles	8.67
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	0.50
P4 cycles	14.67
P5 cycles	14.67
P6 cycles	14.67
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	52.00
Nb loads	32.00
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	P8, P9,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	5.00
Front-end cycles	8.67
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	0.50
P4 cycles	14.67
P5 cycles	14.67
P6 cycles	14.67
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	20.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	52.00
Nb loads	32.00
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	12.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 14.67 cycles (1.36x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 13.33 cycles (1.50x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
24: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	53
nb uops	52
loop length	271
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	2.75	2.75	0.50	14.67	14.67	14.67	14.00	14.00	0.00	0.00	6.00	6.00
cycles	3.00	3.00	2.75	2.75	0.50	14.67	14.67	14.67	14.00	14.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.67
Dispatch	14.67
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f27e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVSXD (%RSI),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VMULSD (%RCX),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
ADD $0x10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD -0xc(%RSI),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD $0x60,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SAL $0x4,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x8(%RSI),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VFMADD213SD -0x60(%RDX),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
SAL $0x4,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD %XMM15,-0x60(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x58(%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x58(%RDX),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,-0x58(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x50(%RCX),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x50(%RDX),%XMM3,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x50(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x48(%RCX),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x48(%RDX),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x48(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x40(%RCX),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x40(%RDX),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x40(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x38(%RCX),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x38(%RDX),%XMM7,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,-0x38(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x30(%RCX),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x30(%RDX),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x28(%RCX),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x28(%RDX),%XMM8,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0x28(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x20(%RCX),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x20(%RDX),%XMM11,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOVSXD -0x4(%RSI),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VMULSD -0x18(%RCX),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x18(%RDX),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x18(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x10(%RCX),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x10(%RDX),%XMM12,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x8(%RCX),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x8(%RDX),%XMM15,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x8(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 40f27e <advancePosition._omp_fn.0+0x1be>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 13.33 cycles (1.50x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
24: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	53
nb uops	52
loop length	271
used x86 registers	7
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	2.75	2.75	0.50	14.67	14.67	14.67	14.00	14.00	0.00	0.00	6.00	6.00
cycles	3.00	3.00	2.75	2.75	0.50	14.67	14.67	14.67	14.00	14.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.67
Dispatch	14.67
DIV/SQRT	20.00
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f27e

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOVSXD (%RSI),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VMULSD (%RCX),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
ADD $0x10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD -0xc(%RSI),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD $0x60,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
SAL $0x4,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x8(%RSI),%R8	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VFMADD213SD -0x60(%RDX),%XMM14,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
SAL $0x4,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD %XMM15,-0x60(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x58(%RCX),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x58(%RDX),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,-0x58(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x50(%RCX),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x50(%RDX),%XMM3,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x50(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x48(%RCX),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x48(%RDX),%XMM4,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x48(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x40(%RCX),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x40(%RDX),%XMM4,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x40(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x38(%RCX),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x38(%RDX),%XMM7,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,-0x38(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x30(%RCX),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VDIVSD 0x8(%RDI,%R8,1),%XMM2,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x30(%RDX),%XMM8,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x28(%RCX),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x28(%RDX),%XMM8,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0x28(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x20(%RCX),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x20(%RDX),%XMM11,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOVSXD -0x4(%RSI),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VMULSD -0x18(%RCX),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	13	5
VFMADD213SD -0x18(%RDX),%XMM12,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x18(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x10(%RCX),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x10(%RDX),%XMM12,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMULSD -0x8(%RCX),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	3	0.50
VFMADD213SD -0x8(%RDX),%XMM15,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x8(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 40f27e <advancePosition._omp_fn.0+0x1be>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.01	-0	1.03	0	0.98	0.01	0.9	0.04	0.78	0.09	0.39	0.33	0.39	0.25

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	1.51	0.52
2x2	4	1.01	2.01	2	0.77	0.5
2x4	8	1.03	4.14	4	0.39	0.46
2x8	16	0.98	7.84	8	0.23	0.46
2x16	32	0.9	14.9	16.5	0.12	0.39
2x32	64	0.78	24.83	32	0.08	0.39
2x64	128	0.39	24.83	64	0.07	0.54
2x96	192	0.39	37.25	96	0.06	0.41

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency