OV - - Loop 86

	Loop Id: 86	Module: exec	Source: ljForce.c:187-216 [...]	Coverage: 6.37%

0x40bc38 CMP	%R13D,%R11D

0x40bc3b JGE	40be86

0x40bc41 MOV	0x20(%R15),%RDI

0x40bc45 LEA	(%R8,%R8,2),%R10

0x40bc49 MOV	0x18(%RDI),%RCX

0x40bc4d LEA	(%RCX,%R12,1),%RAX

0x40bc51 LEA	(%RCX,%R10,1),%RDX

0x40bc55 ADD	%R14,%RCX

0x40bc58 MOV	%RCX,%RSI

0x40bc5b SUB	%RAX,%RSI

0x40bc5e AND	$0x8,%ESI

0x40bc61 JE	40bd20

0x40bc67 VMOVSD	0x8(%RDX),%XMM2

0x40bc6c VSUBSD	0x8(%RAX),%XMM2,%XMM0

0x40bc71 VMOVSD	(%RDX),%XMM1

0x40bc75 VSUBSD	(%RAX),%XMM1,%XMM1

0x40bc79 VMOVSD	0x10(%RDX),%XMM13

0x40bc7e VSUBSD	0x10(%RAX),%XMM13,%XMM2

0x40bc83 VMULSD	%XMM0,%XMM0,%XMM3

0x40bc87 VFMADD231SD	%XMM1,%XMM1,%XMM3

0x40bc8c VFMADD231SD	%XMM2,%XMM2,%XMM3

0x40bc91 VCOMISD	%XMM3,%XMM9

0x40bc95 JB	40bd11

0x40bc97 VCOMISD	%XMM4,%XMM3

0x40bc9b JBE	40bd11

0x40bc9d VDIVSD	%XMM3,%XMM7,%XMM15

0x40bca1 MOV	0x30(%RDI),%RSI

0x40bca5 ADD	%R8,%RSI

0x40bca8 VMULSD	%XMM15,%XMM15,%XMM13

0x40bcad VMULSD	%XMM15,%XMM10,%XMM3

0x40bcb2 VMULSD	%XMM15,%XMM8,%XMM14

0x40bcb7 VMULSD	%XMM3,%XMM13,%XMM3

0x40bcbb VSUBSD	%XMM7,%XMM3,%XMM13

0x40bcbf VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

0x40bcc5 VMOVSD	%XMM13,%XMM13,%XMM15

0x40bcca VFMADD231SD	%XMM6,%XMM13,%XMM5

0x40bccf VMOVSD	%XMM3,%XMM3,%XMM13

0x40bcd3 VFMADD132SD	%XMM11,%XMM12,%XMM13

0x40bcd8 VFMADD213SD	(%RSI),%XMM6,%XMM15

0x40bcdd VMULSD	%XMM13,%XMM3,%XMM3

0x40bce2 VMOVSD	%XMM15,(%RSI)

0x40bce6 MOV	0x28(%RDI),%RSI

0x40bcea ADD	%R10,%RSI

0x40bced VMULSD	%XMM14,%XMM3,%XMM14

0x40bcf2 VFNMADD213SD	(%RSI),%XMM14,%XMM1

0x40bcf7 VFNMADD213SD	0x8(%RSI),%XMM14,%XMM0

0x40bcfd VFNMADD213SD	0x10(%RSI),%XMM2,%XMM14

0x40bd03 VMOVSD	%XMM1,(%RSI)

0x40bd07 VMOVSD	%XMM0,0x8(%RSI)

0x40bd0c VMOVSD	%XMM14,0x10(%RSI)

0x40bd11 ADD	$0x18,%RAX

0x40bd15 CMP	%RAX,%RCX

0x40bd18 JE	40be86

0x40bd1e XCHG	%AX,%AX

  (87) 0x40bd20 VMOVSD	0x8(%RDX),%XMM0

  (87) 0x40bd25 VSUBSD	0x8(%RAX),%XMM0,%XMM0

  (87) 0x40bd2a VMOVSD	(%RDX),%XMM1

  (87) 0x40bd2e VSUBSD	(%RAX),%XMM1,%XMM1

  (87) 0x40bd32 VMOVSD	0x10(%RDX),%XMM2

  (87) 0x40bd37 VSUBSD	0x10(%RAX),%XMM2,%XMM2

  (87) 0x40bd3c VMULSD	%XMM0,%XMM0,%XMM15

  (87) 0x40bd40 VFMADD231SD	%XMM1,%XMM1,%XMM15

  (87) 0x40bd45 VFMADD231SD	%XMM2,%XMM2,%XMM15

  (87) 0x40bd4a VCOMISD	%XMM15,%XMM9

  (87) 0x40bd4f JB	40bdca

  (87) 0x40bd51 VCOMISD	%XMM4,%XMM15

  (87) 0x40bd55 JBE	40bdca

  (87) 0x40bd57 VDIVSD	%XMM15,%XMM7,%XMM3

  (87) 0x40bd5c MOV	0x30(%RDI),%RSI

  (87) 0x40bd60 ADD	%R8,%RSI

  (87) 0x40bd63 VMULSD	%XMM3,%XMM3,%XMM13

  (87) 0x40bd67 VMULSD	%XMM3,%XMM10,%XMM15

  (87) 0x40bd6b VMULSD	%XMM3,%XMM8,%XMM14

  (87) 0x40bd6f VMULSD	%XMM15,%XMM13,%XMM3

  (87) 0x40bd74 VSUBSD	%XMM7,%XMM3,%XMM13

  (87) 0x40bd78 VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

  (87) 0x40bd7e VMOVSD	%XMM13,%XMM13,%XMM15

  (87) 0x40bd83 VFMADD231SD	%XMM6,%XMM13,%XMM5

  (87) 0x40bd88 VMOVSD	%XMM3,%XMM3,%XMM13

  (87) 0x40bd8c VFMADD132SD	%XMM11,%XMM12,%XMM13

  (87) 0x40bd91 VFMADD213SD	(%RSI),%XMM6,%XMM15

  (87) 0x40bd96 VMULSD	%XMM13,%XMM3,%XMM3

  (87) 0x40bd9b VMOVSD	%XMM15,(%RSI)

  (87) 0x40bd9f MOV	0x28(%RDI),%RSI

  (87) 0x40bda3 ADD	%R10,%RSI

  (87) 0x40bda6 VMULSD	%XMM14,%XMM3,%XMM14

  (87) 0x40bdab VFNMADD213SD	(%RSI),%XMM14,%XMM1

  (87) 0x40bdb0 VFNMADD213SD	0x8(%RSI),%XMM14,%XMM0

  (87) 0x40bdb6 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM14

  (87) 0x40bdbc VMOVSD	%XMM1,(%RSI)

  (87) 0x40bdc0 VMOVSD	%XMM0,0x8(%RSI)

  (87) 0x40bdc5 VMOVSD	%XMM14,0x10(%RSI)

  (87) 0x40bdca VMOVSD	0x8(%RDX),%XMM0

  (87) 0x40bdcf VSUBSD	0x20(%RAX),%XMM0,%XMM0

  (87) 0x40bdd4 LEA	0x18(%RAX),%RSI

  (87) 0x40bdd8 VMOVSD	(%RDX),%XMM1

  (87) 0x40bddc VSUBSD	0x18(%RAX),%XMM1,%XMM1

  (87) 0x40bde1 VMOVSD	0x10(%RDX),%XMM2

  (87) 0x40bde6 VSUBSD	0x28(%RAX),%XMM2,%XMM2

  (87) 0x40bdeb VMULSD	%XMM0,%XMM0,%XMM15

  (87) 0x40bdef VFMADD231SD	%XMM1,%XMM1,%XMM15

  (87) 0x40bdf4 VFMADD231SD	%XMM2,%XMM2,%XMM15

  (87) 0x40bdf9 VCOMISD	%XMM15,%XMM9

  (87) 0x40bdfe JB	40be79

  (87) 0x40be00 VCOMISD	%XMM4,%XMM15

  (87) 0x40be04 JBE	40be79

  (87) 0x40be06 VDIVSD	%XMM15,%XMM7,%XMM3

  (87) 0x40be0b MOV	0x30(%RDI),%RAX

  (87) 0x40be0f ADD	%R8,%RAX

  (87) 0x40be12 VMULSD	%XMM3,%XMM3,%XMM13

  (87) 0x40be16 VMULSD	%XMM3,%XMM10,%XMM15

  (87) 0x40be1a VMULSD	%XMM3,%XMM8,%XMM14

  (87) 0x40be1e VMULSD	%XMM15,%XMM13,%XMM3

  (87) 0x40be23 VSUBSD	%XMM7,%XMM3,%XMM13

  (87) 0x40be27 VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

  (87) 0x40be2d VMOVSD	%XMM13,%XMM13,%XMM15

  (87) 0x40be32 VFMADD231SD	%XMM6,%XMM13,%XMM5

  (87) 0x40be37 VMOVSD	%XMM3,%XMM3,%XMM13

  (87) 0x40be3b VFMADD132SD	%XMM11,%XMM12,%XMM13

  (87) 0x40be40 VFMADD213SD	(%RAX),%XMM6,%XMM15

  (87) 0x40be45 VMULSD	%XMM13,%XMM3,%XMM3

  (87) 0x40be4a VMOVSD	%XMM15,(%RAX)

  (87) 0x40be4e MOV	0x28(%RDI),%RAX

  (87) 0x40be52 ADD	%R10,%RAX

  (87) 0x40be55 VMULSD	%XMM14,%XMM3,%XMM14

  (87) 0x40be5a VFNMADD213SD	(%RAX),%XMM14,%XMM1

  (87) 0x40be5f VFNMADD213SD	0x8(%RAX),%XMM14,%XMM0

  (87) 0x40be65 VFNMADD213SD	0x10(%RAX),%XMM2,%XMM14

  (87) 0x40be6b VMOVSD	%XMM1,(%RAX)

  (87) 0x40be6f VMOVSD	%XMM0,0x8(%RAX)

  (87) 0x40be74 VMOVSD	%XMM14,0x10(%RAX)

  (87) 0x40be79 LEA	0x18(%RSI),%RAX

  (87) 0x40be7d CMP	%RAX,%RCX

  (87) 0x40be80 JNE	40bd20

0x40be86 ADD	$0x8,%R8

0x40be8a CMP	%R8,%RBX

0x40be8d JNE	40bc38

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216

--------------------------------------------------------------------------------

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.78
CQA speedup if fully vectorized	4.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	2.13
Front-end cycles	9.50
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.00
P4 cycles	6.33
P5 cycles	6.33
P6 cycles	6.33
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	5.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	15.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	3.16
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	9.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.46

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.78
CQA speedup if fully vectorized	4.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	2.13
Front-end cycles	9.50
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.00
P4 cycles	6.33
P5 cycles	6.33
P6 cycles	6.33
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	5.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	57.00
Nb loads	15.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	3.16
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	9.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	11.46

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,191,197-198,201,206-210,213,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 40 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 8.50 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 2.12 cycles (4.47x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 2 occurrences

Type of elements and instruction set

23 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

13: addition or subtraction (9 inside FMA instructions)
16: multiply (9 inside FMA instructions)
1: divide

The binary loop is loading 120 bytes (15 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	245
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	8.50	8.50	4.00	4.00	3.00	3.00
cycles	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	8.50	8.50	4.00	4.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

5.00

Cycles summary

Front-end	9.50
Dispatch	8.50
DIV/SQRT	5.00
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

13% of peak load performance is reached (12.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.37 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 8.50 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 40bc38

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
CMP %R13D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40be86 <ljForce._omp_fn.1+0x3d6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R8,%R8,2),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%R12,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R10,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R14,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40bd20 <ljForce._omp_fn.1+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x8(%RDX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD 0x8(%RAX),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%RAX),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD 0x10(%RAX),%XMM13,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM1,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VCOMISD %XMM3,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 40bd11 <ljForce._omp_fn.1+0x261>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM4,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 40bd11 <ljForce._omp_fn.1+0x261>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VDIVSD %XMM3,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOV 0x30(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM15,%XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM15,%XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM15,%XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM13,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VSUBSD %XMM7,%XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM13,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD231SD %XMM6,%XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,%XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD132SD %XMM11,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD (%RSI),%XMM6,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM13,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM15,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x28(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM14,%XMM3,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFNMADD213SD (%RSI),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM0,0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM14,0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40be86 <ljForce._omp_fn.1+0x3d6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40bc38 <ljForce._omp_fn.1+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 40 paths individually, rerun with max-paths=40
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 8.50 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 2 occurrences

Type of elements and instruction set

23 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

13: addition or subtraction (9 inside FMA instructions)
16: multiply (9 inside FMA instructions)
1: divide

The binary loop is loading 120 bytes (15 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	245
used x86 registers	14
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	8.50	8.50	4.00	4.00	3.00	3.00
cycles	3.75	3.75	3.75	3.75	3.00	6.33	6.33	6.33	8.50	8.50	4.00	4.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

5.00

Cycles summary

Front-end	9.50
Dispatch	8.50
DIV/SQRT	5.00
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

13% of peak load performance is reached (12.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.37 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40bc38

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
CMP %R13D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40be86 <ljForce._omp_fn.1+0x3d6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x20(%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R8,%R8,2),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%R12,1),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%R10,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R14,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x8,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40bd20 <ljForce._omp_fn.1+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x8(%RDX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD 0x8(%RAX),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD (%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%RAX),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD 0x10(%RAX),%XMM13,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM0,%XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM1,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM2,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VCOMISD %XMM3,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 40bd11 <ljForce._omp_fn.1+0x261>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VCOMISD %XMM4,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 40bd11 <ljForce._omp_fn.1+0x261>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VDIVSD %XMM3,%XMM7,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOV 0x30(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM15,%XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM15,%XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM15,%XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM3,%XMM13,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VSUBSD %XMM7,%XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM13,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD231SD %XMM6,%XMM13,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM3,%XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VFMADD132SD %XMM11,%XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD (%RSI),%XMM6,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM13,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM15,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x28(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD %R10,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULSD %XMM14,%XMM3,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFNMADD213SD (%RSI),%XMM14,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM1,(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM0,0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM14,0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40be86 <ljForce._omp_fn.1+0x3d6>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40bc38 <ljForce._omp_fn.1+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.97	0.16	0.94	0.38	0.9	0.61	0.79	1.17	0.71	1.51	0.56	2.03	0.46	2.23

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	18.42	6.37
2x2	4	0.97	1.95	2	9.42	6.31
2x4	8	0.94	3.76	4	4.84	6.31
2x8	16	0.9	7.19	8	2.43	5.98
2x16	32	0.79	13.04	16.5	1.36	5.6
2x32	64	0.71	22.82	32	0.75	5.26
2x64	128	0.56	35.8	64	0.46	4.61
2x96	192	0.46	44.54	96	0.33	4.16

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency