OV - - Loop 83

	Loop Id: 83	Module: exec	Source: ljForce.c:175-216 [...]	Coverage: 0.03%

0x40bb77 MOV	-0x64(%RBP),%R9D

0x40bb7b MOV	(%R14,%RAX,4),%R8D

0x40bb7f TEST	%R9D,%R9D

0x40bb82 JLE	40beba

0x40bb88 MOV	0x80(%R13),%R11

0x40bb8f MOV	%EAX,%ESI

0x40bb91 LEA	(%R8,%RCX,1),%R10D

0x40bb95 MOV	%ECX,-0x7c(%RBP)

0x40bb98 SAL	$0x6,%ESI

0x40bb9b MOV	-0x70(%RBP),%RBX

0x40bb9f LEA	-0x1(%R10),%R9D

0x40bba3 MOV	%R13,-0x78(%RBP)

0x40bba7 MOVSXD	%ESI,%R8

0x40bbaa MOV	(%R11,%RAX,8),%RDX

0x40bbae SUB	%ESI,%R9D

0x40bbb1 MOV	%R14,-0x48(%RBP)

0x40bbb5 LEA	(,%R8,8),%RDI

0x40bbbd MOV	%R10D,-0x5c(%RBP)

0x40bbc1 VMOVSD	0x6517(%RIP),%XMM12

0x40bbc9 ADD	%RDX,%RBX

0x40bbcc MOV	%RDI,-0x58(%RBP)

0x40bbd0 MOV	%ESI,-0x60(%RBP)

0x40bbd3 MOV	%RAX,-0x88(%RBP)

0x40bbda MOV	%RBX,-0x50(%RBP)

0x40bbde LEA	0x1(%R8,%R9,1),%RBX

0x40bbe3 MOV	%R12,%R9

0x40bbe6 SAL	$0x3,%RBX

  (85) 0x40bbea MOV	(%RDX),%R11D

  (85) 0x40bbed TEST	%R11D,%R11D

  (85) 0x40bbf0 JS	40bf20

  (85) 0x40bbf6 MOV	-0x48(%RBP),%R13

  (85) 0x40bbfa MOVSXD	%R11D,%R12

  (85) 0x40bbfd MOV	-0x60(%RBP),%EAX

  (85) 0x40bc00 MOV	(%R13,%R12,4),%R14D

  (85) 0x40bc05 CMP	%EAX,-0x5c(%RBP)

  (85) 0x40bc08 JLE	40be97

  (85) 0x40bc0e LEA	(%R12,%R12,2),%R12

  (85) 0x40bc12 MOV	%RDX,-0x40(%RBP)

  (85) 0x40bc16 SAL	$0x6,%R11D

  (85) 0x40bc1a LEA	(%R14,%R14,2),%RCX

  (85) 0x40bc1e SAL	$0x9,%R12

  (85) 0x40bc22 MOV	-0x58(%RBP),%R8

  (85) 0x40bc26 LEA	(%R14,%R11,1),%R13D

  (85) 0x40bc2a VXORPD	%XMM4,%XMM4,%XMM4

  (85) 0x40bc2e LEA	(%R12,%RCX,8),%R14

  (85) 0x40bc32 NOPW	(%RAX,%RAX,1)

    (86) 0x40bc38 CMP	%R13D,%R11D

    (86) 0x40bc3b JGE	40be86

    (86) 0x40bc41 MOV	0x20(%R15),%RDI

    (86) 0x40bc45 LEA	(%R8,%R8,2),%R10

    (86) 0x40bc49 MOV	0x18(%RDI),%RCX

    (86) 0x40bc4d LEA	(%RCX,%R12,1),%RAX

    (86) 0x40bc51 LEA	(%RCX,%R10,1),%RDX

    (86) 0x40bc55 ADD	%R14,%RCX

    (86) 0x40bc58 MOV	%RCX,%RSI

    (86) 0x40bc5b SUB	%RAX,%RSI

    (86) 0x40bc5e AND	$0x8,%ESI

    (86) 0x40bc61 JE	40bd20

    (86) 0x40bc67 VMOVSD	0x8(%RDX),%XMM2

    (86) 0x40bc6c VSUBSD	0x8(%RAX),%XMM2,%XMM0

    (86) 0x40bc71 VMOVSD	(%RDX),%XMM1

    (86) 0x40bc75 VSUBSD	(%RAX),%XMM1,%XMM1

    (86) 0x40bc79 VMOVSD	0x10(%RDX),%XMM13

    (86) 0x40bc7e VSUBSD	0x10(%RAX),%XMM13,%XMM2

    (86) 0x40bc83 VMULSD	%XMM0,%XMM0,%XMM3

    (86) 0x40bc87 VFMADD231SD	%XMM1,%XMM1,%XMM3

    (86) 0x40bc8c VFMADD231SD	%XMM2,%XMM2,%XMM3

    (86) 0x40bc91 VCOMISD	%XMM3,%XMM9

    (86) 0x40bc95 JB	40bd11

    (86) 0x40bc97 VCOMISD	%XMM4,%XMM3

    (86) 0x40bc9b JBE	40bd11

    (86) 0x40bc9d VDIVSD	%XMM3,%XMM7,%XMM15

    (86) 0x40bca1 MOV	0x30(%RDI),%RSI

    (86) 0x40bca5 ADD	%R8,%RSI

    (86) 0x40bca8 VMULSD	%XMM15,%XMM15,%XMM13

    (86) 0x40bcad VMULSD	%XMM15,%XMM10,%XMM3

    (86) 0x40bcb2 VMULSD	%XMM15,%XMM8,%XMM14

    (86) 0x40bcb7 VMULSD	%XMM3,%XMM13,%XMM3

    (86) 0x40bcbb VSUBSD	%XMM7,%XMM3,%XMM13

    (86) 0x40bcbf VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

    (86) 0x40bcc5 VMOVSD	%XMM13,%XMM13,%XMM15

    (86) 0x40bcca VFMADD231SD	%XMM6,%XMM13,%XMM5

    (86) 0x40bccf VMOVSD	%XMM3,%XMM3,%XMM13

    (86) 0x40bcd3 VFMADD132SD	%XMM11,%XMM12,%XMM13

    (86) 0x40bcd8 VFMADD213SD	(%RSI),%XMM6,%XMM15

    (86) 0x40bcdd VMULSD	%XMM13,%XMM3,%XMM3

    (86) 0x40bce2 VMOVSD	%XMM15,(%RSI)

    (86) 0x40bce6 MOV	0x28(%RDI),%RSI

    (86) 0x40bcea ADD	%R10,%RSI

    (86) 0x40bced VMULSD	%XMM14,%XMM3,%XMM14

    (86) 0x40bcf2 VFNMADD213SD	(%RSI),%XMM14,%XMM1

    (86) 0x40bcf7 VFNMADD213SD	0x8(%RSI),%XMM14,%XMM0

    (86) 0x40bcfd VFNMADD213SD	0x10(%RSI),%XMM2,%XMM14

    (86) 0x40bd03 VMOVSD	%XMM1,(%RSI)

    (86) 0x40bd07 VMOVSD	%XMM0,0x8(%RSI)

    (86) 0x40bd0c VMOVSD	%XMM14,0x10(%RSI)

    (86) 0x40bd11 ADD	$0x18,%RAX

    (86) 0x40bd15 CMP	%RAX,%RCX

    (86) 0x40bd18 JE	40be86

    (86) 0x40bd1e XCHG	%AX,%AX

      (87) 0x40bd20 VMOVSD	0x8(%RDX),%XMM0

      (87) 0x40bd25 VSUBSD	0x8(%RAX),%XMM0,%XMM0

      (87) 0x40bd2a VMOVSD	(%RDX),%XMM1

      (87) 0x40bd2e VSUBSD	(%RAX),%XMM1,%XMM1

      (87) 0x40bd32 VMOVSD	0x10(%RDX),%XMM2

      (87) 0x40bd37 VSUBSD	0x10(%RAX),%XMM2,%XMM2

      (87) 0x40bd3c VMULSD	%XMM0,%XMM0,%XMM15

      (87) 0x40bd40 VFMADD231SD	%XMM1,%XMM1,%XMM15

      (87) 0x40bd45 VFMADD231SD	%XMM2,%XMM2,%XMM15

      (87) 0x40bd4a VCOMISD	%XMM15,%XMM9

      (87) 0x40bd4f JB	40bdca

      (87) 0x40bd51 VCOMISD	%XMM4,%XMM15

      (87) 0x40bd55 JBE	40bdca

      (87) 0x40bd57 VDIVSD	%XMM15,%XMM7,%XMM3

      (87) 0x40bd5c MOV	0x30(%RDI),%RSI

      (87) 0x40bd60 ADD	%R8,%RSI

      (87) 0x40bd63 VMULSD	%XMM3,%XMM3,%XMM13

      (87) 0x40bd67 VMULSD	%XMM3,%XMM10,%XMM15

      (87) 0x40bd6b VMULSD	%XMM3,%XMM8,%XMM14

      (87) 0x40bd6f VMULSD	%XMM15,%XMM13,%XMM3

      (87) 0x40bd74 VSUBSD	%XMM7,%XMM3,%XMM13

      (87) 0x40bd78 VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

      (87) 0x40bd7e VMOVSD	%XMM13,%XMM13,%XMM15

      (87) 0x40bd83 VFMADD231SD	%XMM6,%XMM13,%XMM5

      (87) 0x40bd88 VMOVSD	%XMM3,%XMM3,%XMM13

      (87) 0x40bd8c VFMADD132SD	%XMM11,%XMM12,%XMM13

      (87) 0x40bd91 VFMADD213SD	(%RSI),%XMM6,%XMM15

      (87) 0x40bd96 VMULSD	%XMM13,%XMM3,%XMM3

      (87) 0x40bd9b VMOVSD	%XMM15,(%RSI)

      (87) 0x40bd9f MOV	0x28(%RDI),%RSI

      (87) 0x40bda3 ADD	%R10,%RSI

      (87) 0x40bda6 VMULSD	%XMM14,%XMM3,%XMM14

      (87) 0x40bdab VFNMADD213SD	(%RSI),%XMM14,%XMM1

      (87) 0x40bdb0 VFNMADD213SD	0x8(%RSI),%XMM14,%XMM0

      (87) 0x40bdb6 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM14

      (87) 0x40bdbc VMOVSD	%XMM1,(%RSI)

      (87) 0x40bdc0 VMOVSD	%XMM0,0x8(%RSI)

      (87) 0x40bdc5 VMOVSD	%XMM14,0x10(%RSI)

      (87) 0x40bdca VMOVSD	0x8(%RDX),%XMM0

      (87) 0x40bdcf VSUBSD	0x20(%RAX),%XMM0,%XMM0

      (87) 0x40bdd4 LEA	0x18(%RAX),%RSI

      (87) 0x40bdd8 VMOVSD	(%RDX),%XMM1

      (87) 0x40bddc VSUBSD	0x18(%RAX),%XMM1,%XMM1

      (87) 0x40bde1 VMOVSD	0x10(%RDX),%XMM2

      (87) 0x40bde6 VSUBSD	0x28(%RAX),%XMM2,%XMM2

      (87) 0x40bdeb VMULSD	%XMM0,%XMM0,%XMM15

      (87) 0x40bdef VFMADD231SD	%XMM1,%XMM1,%XMM15

      (87) 0x40bdf4 VFMADD231SD	%XMM2,%XMM2,%XMM15

      (87) 0x40bdf9 VCOMISD	%XMM15,%XMM9

      (87) 0x40bdfe JB	40be79

      (87) 0x40be00 VCOMISD	%XMM4,%XMM15

      (87) 0x40be04 JBE	40be79

      (87) 0x40be06 VDIVSD	%XMM15,%XMM7,%XMM3

      (87) 0x40be0b MOV	0x30(%RDI),%RAX

      (87) 0x40be0f ADD	%R8,%RAX

      (87) 0x40be12 VMULSD	%XMM3,%XMM3,%XMM13

      (87) 0x40be16 VMULSD	%XMM3,%XMM10,%XMM15

      (87) 0x40be1a VMULSD	%XMM3,%XMM8,%XMM14

      (87) 0x40be1e VMULSD	%XMM15,%XMM13,%XMM3

      (87) 0x40be23 VSUBSD	%XMM7,%XMM3,%XMM13

      (87) 0x40be27 VFMSUB213SD	-0x38(%RBP),%XMM3,%XMM13

      (87) 0x40be2d VMOVSD	%XMM13,%XMM13,%XMM15

      (87) 0x40be32 VFMADD231SD	%XMM6,%XMM13,%XMM5

      (87) 0x40be37 VMOVSD	%XMM3,%XMM3,%XMM13

      (87) 0x40be3b VFMADD132SD	%XMM11,%XMM12,%XMM13

      (87) 0x40be40 VFMADD213SD	(%RAX),%XMM6,%XMM15

      (87) 0x40be45 VMULSD	%XMM13,%XMM3,%XMM3

      (87) 0x40be4a VMOVSD	%XMM15,(%RAX)

      (87) 0x40be4e MOV	0x28(%RDI),%RAX

      (87) 0x40be52 ADD	%R10,%RAX

      (87) 0x40be55 VMULSD	%XMM14,%XMM3,%XMM14

      (87) 0x40be5a VFNMADD213SD	(%RAX),%XMM14,%XMM1

      (87) 0x40be5f VFNMADD213SD	0x8(%RAX),%XMM14,%XMM0

      (87) 0x40be65 VFNMADD213SD	0x10(%RAX),%XMM2,%XMM14

      (87) 0x40be6b VMOVSD	%XMM1,(%RAX)

      (87) 0x40be6f VMOVSD	%XMM0,0x8(%RAX)

      (87) 0x40be74 VMOVSD	%XMM14,0x10(%RAX)

      (87) 0x40be79 LEA	0x18(%RSI),%RAX

      (87) 0x40be7d CMP	%RAX,%RCX

      (87) 0x40be80 JNE	40bd20

    (86) 0x40be86 ADD	$0x8,%R8

    (86) 0x40be8a CMP	%R8,%RBX

    (86) 0x40be8d JNE	40bc38

  (85) 0x40be93 MOV	-0x40(%RBP),%RDX

  (85) 0x40be97 ADD	$0x4,%RDX

  (85) 0x40be9b CMP	%RDX,-0x50(%RBP)

  (85) 0x40be9f JNE	40bbea

0x40bea5 MOV	-0x78(%RBP),%R13

0x40bea9 MOV	-0x48(%RBP),%R14

0x40bead MOV	%R9,%R12

0x40beb0 MOV	-0x7c(%RBP),%ECX

0x40beb3 MOV	-0x88(%RBP),%RAX

0x40beba INC	%RAX

0x40bebd ADD	$0x40,%ECX

0x40bec0 CMP	%EAX,-0x68(%RBP)

0x40bec3 JG	40bb77

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 175 - 216

--------------------------------------------------------------------------------

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	2.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187,ljForce.c:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.08
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.08
CQA cycles if fully vectorized	0.42
Front-end cycles	2.92
DIV/SQRT cycles	1.88
P0 cycles	1.88
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	0.75
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.50
Nb uops	17.50
Nb loads	4.50
Nb stores	4.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.34
Bytes prefetched	0.00
Bytes loaded	26.00
Bytes stored	26.00
Stride 0	1.50
Stride 1	0.00
Stride n	0.00
Stride unknown	2.50
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	10.16
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P5, P6, P7,
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187,ljForce.c:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.71
Front-end cycles	4.67
DIV/SQRT cycles	2.75
P0 cycles	2.75
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	0.50
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	28.00
Nb loads	6.00
Nb stores	8.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.40
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	52.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	10.16
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:175-175,ljForce.c:178-180,ljForce.c:187-187,ljForce.c:213-213
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.17
CQA cycles if no scalar integer	1.17
CQA cycles if FP arith vectorized	1.17
CQA cycles if fully vectorized	0.13
Front-end cycles	1.17
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	7.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.29
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:175,178-180,187,213.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.08 to 0.42 cycles (7.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 26 bytes. The binary loop is storing 26 bytes.

General properties

nb instructions	17.50
nb uops	17.50
loop length	73.50
used x86 registers	10
used mmx registers	0
used xmm registers	0.50
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.92 cycles
front end	2.92 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.88	1.88	1.75	1.75	0.75	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.88	1.88	1.75	1.75	0.75	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.92
Dispatch	3.00
Data deps.	1.00
Overall L1	3.08

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.08 cycles. At this rate:

9% of peak load performance is reached (9.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 1.50 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.71 cycles (7.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.67 cycles (1.07x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 52 bytes.

General properties

nb instructions	27
nb uops	28
loop length	115
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.67 cycles
front end	4.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	0.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.75	2.75	2.50	2.50	0.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.67
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40bb77

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0x64(%RBP),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%R14,%RAX,4),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R9D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 40beba <ljForce._omp_fn.1+0x40a>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x80(%R13),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
LEA (%R8,%RCX,1),%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ECX,-0x7c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOV -0x70(%RBP),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA -0x1(%R10),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R13,-0x78(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVSXD %ESI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%R11,%RAX,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SUB %ESI,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA (,%R8,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R10D,-0x5c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
VMOVSD 0x6517(%RIP),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
ADD %RDX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %ESI,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RBX,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA 0x1(%R8,%R9,1),%RBX	2	0	0	0.50	0.50	0	0.33	0.33	0.33	2	0.50
MOV %R12,%R9	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	1	0.50

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:175-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.17 to 0.12 cycles (9.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	8
nb uops	7
loop length	32
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.17 cycles
front end	1.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.17
Dispatch	1.00
Data deps.	1.00
Overall L1	1.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.17 cycles. At this rate:

10% of peak load performance is reached (10.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.17 to 1.00 cycles (1.17x speedup).

ASM code

In the binary file, the address of the loop is: 40bb77

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0x64(%RBP),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%R14,%RAX,4),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R9D,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 40beba <ljForce._omp_fn.1+0x40a>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
INC %RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x40,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %EAX,-0x68(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JG 40bb77 <ljForce._omp_fn.1+0xc7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.83	0.01	1.25	0	1.25	0	0.61	0.01	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.1	0.03
2x2	4	0.83	1.67	2	0.07	0.04
2x4	8	1.25	5	4	0.02	0.02
2x8	16	1.25	10	8	0.03	0.03
2x16	32	0.61	10	16.5	0.01	0.02
2x32	64	1	1	32	0.01	0.02
2x64	122	1	1	64	0.01	0.01
2x96	175	1	1	96	0.01	0.02

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency