OV - - Loop 65

	Loop Id: 65	Module: exec	Source: initAtoms.c:197-202	Coverage: 0.01%

0x409380 MOV	0x8(%RCX),%R11    [11]

0x409384 MOV	$0x1c9,%ESI

0x409389 LEA	(%R14,%R14,2),%RBX

0x40938d INC	%R15D

0x409390 ADD	%RBX,%RBX

0x409393 MOV	(%R11,%R14,1),%EDI    [5]

0x409397 ADD	$0x4,%R14

0x40939b CALL	40ef10 <mkSeed>

0x4093a0 LEA	-0x38(%RBP),%RDI

0x4093a4 MOV	%RAX,-0x38(%RBP)    [9]

0x4093a8 CALL	40eec0 <lcg61>

0x4093ad MOV	0x20(%R12),%RAX    [1]

0x4093b2 VMOVSD	-0x48(%RBP),%XMM1    [9]

0x4093b7 LEA	-0x38(%RBP),%RDI

0x4093bb VMOVSD	0x8945(%RIP),%XMM2    [6]

0x4093c3 VFMADD132SD	0x8724(%RIP),%XMM2,%XMM0    [6]

0x4093cc MOV	0x18(%RAX),%RAX    [4]

0x4093d0 ADD	%RBX,%RAX

0x4093d3 VFMADD213SD	(%RAX),%XMM1,%XMM0    [3]

0x4093d8 VMOVSD	%XMM0,(%RAX)    [3]

0x4093dc CALL	40eec0 <lcg61>

0x4093e1 MOV	0x20(%R12),%RDX    [1]

0x4093e6 VMOVSD	-0x48(%RBP),%XMM4    [9]

0x4093eb LEA	-0x38(%RBP),%RDI

0x4093ef VMOVSD	0x8911(%RIP),%XMM3    [6]

0x4093f7 VFMADD132SD	0x86f0(%RIP),%XMM3,%XMM0    [6]

0x409400 MOV	0x18(%RDX),%RAX    [4]

0x409404 ADD	%RBX,%RAX

0x409407 VFMADD213SD	0x8(%RAX),%XMM4,%XMM0    [10]

0x40940d VMOVSD	%XMM0,0x8(%RAX)    [10]

0x409412 CALL	40eec0 <lcg61>

0x409417 MOV	0x20(%R12),%RCX    [1]

0x40941c VMOVSD	-0x48(%RBP),%XMM7    [9]

0x409421 VMOVSD	0x88df(%RIP),%XMM6    [6]

0x409429 MOV	0x18(%R12),%RDI    [1]

0x40942e VFMADD132SD	0x86b9(%RIP),%XMM6,%XMM0    [6]

0x409437 ADD	0x18(%RCX),%RBX    [4]

0x40943b VFMADD213SD	0x10(%RBX),%XMM7,%XMM0    [2]

0x409441 MOV	0x78(%RDI),%RSI    [7]

0x409445 VMOVSD	%XMM0,0x10(%RBX)    [2]

0x40944a CMP	%R15D,(%RSI,%R13,1)    [8]

0x40944e JG	409380

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 197 - 202

--------------------------------------------------------------------------------

197:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

198:       {

199:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 457);

200:          s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta;

201:          s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta;

202:          s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.53
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.32
Bottlenecks
Function	randomDisplacements._omp_fn.0
Source	initAtoms.c:197-202
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	3.00
Front-end cycles	7.50
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	2.50
P4 cycles	10.33
P5 cycles	10.33
P6 cycles	10.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.67
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	3.00
Stride 1	1.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	3.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.53
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.32
Bottlenecks
Function	randomDisplacements._omp_fn.0
Source	initAtoms.c:197-202
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	3.00
Front-end cycles	7.50
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	2.50
P4 cycles	10.33
P5 cycles	10.33
P6 cycles	10.33
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	0.00
Inter-iter dependencies cycles	24
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	45.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	6.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.67
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	32.00
Stride 0	3.00
Stride 1	1.00
Stride n	1.00
Stride unknown	2.00
Stride indirect	3.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	randomDisplacements._omp_fn.0
Source file and lines	initAtoms.c:197-202
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:197-202.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 3.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

lcg61: 3 occurrences
mkSeed: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	42
nb uops	45
loop length	212
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.25	3.25	2.50	10.33	10.33	10.33	3.00	3.00	0.00	0.00	1.50	1.50
cycles	3.50	3.50	3.25	3.25	2.50	10.33	10.33	10.33	3.00	3.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	7.50
Dispatch	10.33
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

7% of peak load performance is reached (7.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 409380

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOV 0x8(%RCX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV $0x1c9,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%R14,%R14,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV (%R11,%R14,1),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD $0x4,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 40ef10 <mkSeed>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8945(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x8724(%RIP),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SD (%RAX),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8911(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x86f0(%RIP),%XMM3,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x18(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SD 0x8(%RAX),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,0x8(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x88df(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV 0x18(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VFMADD132SD 0x86b9(%RIP),%XMM6,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD 0x18(%RCX),%RBX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VFMADD213SD 0x10(%RBX),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x78(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD %XMM0,0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R15D,(%RSI,%R13,1)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JG 409380 <randomDisplacements._omp_fn.0+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	randomDisplacements._omp_fn.0
Source file and lines	initAtoms.c:197-202
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 3.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 6 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

lcg61: 3 occurrences
mkSeed: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

6: addition or subtraction (all inside FMA instructions)
6: multiply (all inside FMA instructions)

The binary loop is loading 176 bytes (22 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	42
nb uops	45
loop length	212
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.50	3.50	3.25	3.25	2.50	10.33	10.33	10.33	3.00	3.00	0.00	0.00	1.50	1.50
cycles	3.50	3.50	3.25	3.25	2.50	10.33	10.33	10.33	3.00	3.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	24.00

Cycles summary

Front-end	7.50
Dispatch	10.33
Data deps.	24.00
Overall L1	24.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

7% of peak load performance is reached (7.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 409380

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
MOV 0x8(%RCX),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV $0x1c9,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA (%R14,%R14,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD %RBX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV (%R11,%R14,1),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD $0x4,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CALL 40ef10 <mkSeed>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8945(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x8724(%RIP),%XMM2,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SD (%RAX),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
LEA -0x38(%RBP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8911(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD132SD 0x86f0(%RIP),%XMM3,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x18(%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
ADD %RBX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VFMADD213SD 0x8(%RAX),%XMM4,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM0,0x8(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CALL 40eec0 <lcg61>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
MOV 0x20(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD -0x48(%RBP),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VMOVSD 0x88df(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOV 0x18(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VFMADD132SD 0x86b9(%RIP),%XMM6,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD 0x18(%RCX),%RBX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
VFMADD213SD 0x10(%RBX),%XMM7,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
MOV 0x78(%RDI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
VMOVSD %XMM0,0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %R15D,(%RSI,%R13,1)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
JG 409380 <randomDisplacements._omp_fn.0+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	0.5	0.01	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.02	0.01
2x2	4	1	2	2	0.01	0.01
2x4	7	0.5	2	4	0.01	0.01
2x8	14	1	1	8	0.02	0.01
2x16	20	1	1	16.5	0	0.01
2x32	19	1	1	32	0.01	0.01
2x64	17	1	1	64	0	0.01
2x96	107	1	1	96	0	0.05

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency