OV - - Loop 54

	Loop Id: 54	Module: exec	Source: haloExchange.c:633-642	Coverage: 0.12%

0x4088c0 MOV	(%RAX),%R12D    [4]

0x4088c3 VMOVSD	0x8(%RAX),%XMM4    [4]

0x4088c8 LEA	0x1(%RDI),%R10

0x4088cc ADD	$0x70,%RAX

0x4088d0 ADD	$0x30,%RSI

0x4088d4 ADD	$0x30,%RCX

0x4088d8 MOV	%R12D,(%R15,%RDI,4)    [8]

0x4088dc MOV	-0x6c(%RAX),%EBX    [5]

0x4088df MOV	%EBX,(%R11,%RDI,4)    [3]

0x4088e3 MOV	-0x38(%RAX),%R9D    [5]

0x4088e7 ADD	$0x2,%RDI

0x4088eb VMOVSD	%XMM4,-0x30(%RSI)    [1]

0x4088f0 VMOVSD	-0x60(%RAX),%XMM5    [5]

0x4088f5 VMOVSD	%XMM5,-0x28(%RSI)    [1]

0x4088fa VMOVSD	-0x58(%RAX),%XMM6    [5]

0x4088ff VMOVSD	%XMM6,-0x20(%RSI)    [1]

0x408904 VMOVSD	-0x50(%RAX),%XMM7    [5]

0x408909 VMOVSD	%XMM7,-0x30(%RCX)    [7]

0x40890e VMOVSD	-0x48(%RAX),%XMM8    [5]

0x408913 VMOVSD	%XMM8,-0x28(%RCX)    [7]

0x408918 VMOVSD	-0x40(%RAX),%XMM9    [5]

0x40891d VMOVSD	%XMM9,-0x20(%RCX)    [7]

0x408922 VMOVSD	-0x30(%RAX),%XMM10    [5]

0x408927 MOV	%R9D,(%R15,%R10,4)    [2]

0x40892b MOV	-0x34(%RAX),%R8D    [5]

0x40892f MOV	%R8D,(%R11,%R10,4)    [6]

0x408933 VMOVSD	%XMM10,-0x18(%RSI)    [1]

0x408938 VMOVSD	-0x28(%RAX),%XMM11    [5]

0x40893d VMOVSD	%XMM11,-0x10(%RSI)    [1]

0x408942 VMOVSD	-0x20(%RAX),%XMM12    [5]

0x408947 VMOVSD	%XMM12,-0x8(%RSI)    [1]

0x40894c VMOVSD	-0x18(%RAX),%XMM13    [5]

0x408951 VMOVSD	%XMM13,-0x18(%RCX)    [7]

0x408956 VMOVSD	-0x10(%RAX),%XMM14    [5]

0x40895b VMOVSD	%XMM14,-0x10(%RCX)    [7]

0x408960 VMOVSD	-0x8(%RAX),%XMM15    [5]

0x408965 VMOVSD	%XMM15,-0x8(%RCX)    [7]

0x40896a CMP	%EDI,%R13D

0x40896d JG	4088c0

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642

--------------------------------------------------------------------------------

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	1.75
Front-end cycles	6.33
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	38.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	2.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	1.75
Front-end cycles	6.33
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	38.00
Nb loads	16.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	2.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 1.75 cycles (6.10x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 6.33 cycles (1.68x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 112 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	39
nb uops	38
loop length	179
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.33 cycles
front end	6.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.50	1.25	1.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	6.00	6.00
cycles	1.50	1.50	1.25	1.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.33
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4088c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV (%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD 0x8(%RAX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA 0x1(%RDI),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x70,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x30,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x30,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R12D,(%R15,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x6c(%RAX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EBX,(%R11,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x38(%RAX),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x30(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x60(%RAX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM5,-0x28(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x58(%RAX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM6,-0x20(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x50(%RAX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM7,-0x30(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x48(%RAX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM8,-0x28(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x40(%RAX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM9,-0x20(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x30(%RAX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R9D,(%R15,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x34(%RAX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%R11,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x28(%RAX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x20(%RAX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x18(%RAX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM13,-0x18(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x10(%RAX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM14,-0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x8(%RAX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM15,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
CMP %EDI,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JG 4088c0 <sortAtomsInCell+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 6.33 cycles (1.68x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 112 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	39
nb uops	38
loop length	179
used x86 registers	12
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.33 cycles
front end	6.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.50	1.25	1.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	6.00	6.00
cycles	1.50	1.50	1.25	1.25	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.33
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4088c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV (%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD 0x8(%RAX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
LEA 0x1(%RDI),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x70,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x30,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x30,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R12D,(%R15,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x6c(%RAX),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EBX,(%R11,%RDI,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x38(%RAX),%R9D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
ADD $0x2,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD %XMM4,-0x30(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x60(%RAX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM5,-0x28(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x58(%RAX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM6,-0x20(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x50(%RAX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM7,-0x30(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x48(%RAX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM8,-0x28(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x40(%RAX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM9,-0x20(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x30(%RAX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %R9D,(%R15,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV -0x34(%RAX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%R11,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
VMOVSD %XMM10,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x28(%RAX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM11,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x20(%RAX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM12,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x18(%RAX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM13,-0x18(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x10(%RAX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM14,-0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD -0x8(%RAX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM15,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
CMP %EDI,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JG 4088c0 <sortAtomsInCell+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.39	0.18	0.24	0.36	0.11	0.83	0.08	0.99	0.06	1.05	0.04	1.25	0.03	1.21

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.41	0.12
2x2	4	0.39	0.77	2	0.83	0.3
2x4	8	0.24	0.94	4	0.48	0.47
2x8	16	0.11	0.85	8	0.74	0.93
2x16	32	0.08	1.26	16.5	0.44	1.07
2x32	64	0.06	2	32	0.3	1.12
2x64	128	0.04	2.43	64	0.21	1.3
2x96	192	0.03	2.83	96	0.2	1.25

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency