OV - - Function ljForce._omp

	Function: ljForce._omp_fn.0	Module: exec	Source: ljForce.c:157-161 [...]	Coverage: 0.38%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 161

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

0x40b7a0 PUSH	%RBP

0x40b7a1 MOV	%RSP,%RBP

0x40b7a4 PUSH	%R12

0x40b7a6 MOV	%RDI,%R12

0x40b7a9 PUSH	%RBX

0x40b7aa CALL	403060 <omp_get_num_threads@plt>

0x40b7af MOV	%EAX,%EBX

0x40b7b1 CALL	403160 <omp_get_thread_num@plt>

0x40b7b6 MOV	%EAX,%ECX

0x40b7b8 MOV	0x8(%R12),%EAX

0x40b7bd CLTD

0x40b7be IDIV	%EBX

0x40b7c0 CMP	%EDX,%ECX

0x40b7c2 JL	40ba98

0x40b7c8 IMUL	%EAX,%ECX

0x40b7cb ADD	%ECX,%EDX

0x40b7cd LEA	(%RAX,%RDX,1),%ESI

0x40b7d0 CMP	%ESI,%EDX

0x40b7d2 JGE	40ba90

0x40b7d8 MOV	(%R12),%RDI

0x40b7dc MOVSXD	%EDX,%R10

0x40b7df MOV	%EAX,%EAX

0x40b7e1 ADD	%R10,%RAX

0x40b7e4 LEA	(%R10,%R10,2),%R11

0x40b7e8 MOV	0x20(%RDI),%R8

0x40b7ec MOV	0x30(%R8),%R9

0x40b7f0 MOV	0x28(%R8),%R12

0x40b7f4 LEA	(%R9,%RAX,8),%RDX

0x40b7f8 LEA	(%R9,%R10,8),%RCX

0x40b7fc MOV	%RDX,%RSI

0x40b7ff LEA	(%R12,%R11,8),%RBX

0x40b803 SUB	%RCX,%RSI

0x40b806 SUB	$0x8,%RSI

0x40b80a SHR	$0x3,%RSI

0x40b80e INC	%RSI

0x40b811 AND	$0x7,%ESI

0x40b814 JE	40b968

0x40b81a CMP	$0x1,%RSI

0x40b81e JE	40b938

0x40b824 CMP	$0x2,%RSI

0x40b828 JE	40b911

0x40b82e CMP	$0x3,%RSI

0x40b832 JE	40b8ea

0x40b838 CMP	$0x4,%RSI

0x40b83c JE	40b8c3

0x40b842 CMP	$0x5,%RSI

0x40b846 JE	40b89c

0x40b848 CMP	$0x6,%RSI

0x40b84c JE	40b875

0x40b84e MOVQ	$0,(%RBX)

0x40b855 ADD	$0x8,%RCX

0x40b859 ADD	$0x18,%RBX

0x40b85d MOVQ	$0,-0x10(%RBX)

0x40b865 MOVQ	$0,-0x8(%RBX)

0x40b86d MOVQ	$0,-0x8(%RCX)

0x40b875 MOVQ	$0,(%RBX)

0x40b87c ADD	$0x8,%RCX

0x40b880 ADD	$0x18,%RBX

0x40b884 MOVQ	$0,-0x10(%RBX)

0x40b88c MOVQ	$0,-0x8(%RBX)

0x40b894 MOVQ	$0,-0x8(%RCX)

0x40b89c MOVQ	$0,(%RBX)

0x40b8a3 ADD	$0x8,%RCX

0x40b8a7 ADD	$0x18,%RBX

0x40b8ab MOVQ	$0,-0x10(%RBX)

0x40b8b3 MOVQ	$0,-0x8(%RBX)

0x40b8bb MOVQ	$0,-0x8(%RCX)

0x40b8c3 MOVQ	$0,(%RBX)

0x40b8ca ADD	$0x8,%RCX

0x40b8ce ADD	$0x18,%RBX

0x40b8d2 MOVQ	$0,-0x10(%RBX)

0x40b8da MOVQ	$0,-0x8(%RBX)

0x40b8e2 MOVQ	$0,-0x8(%RCX)

0x40b8ea MOVQ	$0,(%RBX)

0x40b8f1 ADD	$0x8,%RCX

0x40b8f5 ADD	$0x18,%RBX

0x40b8f9 MOVQ	$0,-0x10(%RBX)

0x40b901 MOVQ	$0,-0x8(%RBX)

0x40b909 MOVQ	$0,-0x8(%RCX)

0x40b911 MOVQ	$0,(%RBX)

0x40b918 ADD	$0x8,%RCX

0x40b91c ADD	$0x18,%RBX

0x40b920 MOVQ	$0,-0x10(%RBX)

0x40b928 MOVQ	$0,-0x8(%RBX)

0x40b930 MOVQ	$0,-0x8(%RCX)

0x40b938 MOVQ	$0,(%RBX)

0x40b93f ADD	$0x8,%RCX

0x40b943 ADD	$0x18,%RBX

0x40b947 MOVQ	$0,-0x10(%RBX)

0x40b94f MOVQ	$0,-0x8(%RBX)

0x40b957 MOVQ	$0,-0x8(%RCX)

0x40b95f CMP	%RDX,%RCX

0x40b962 JE	40ba90

(82) 0x40b968 MOVQ	$0,(%RBX)

(82) 0x40b96f ADD	$0x40,%RCX

(82) 0x40b973 ADD	$0xc0,%RBX

(82) 0x40b97a MOVQ	$0,-0xb8(%RBX)

(82) 0x40b985 MOVQ	$0,-0xb0(%RBX)

(82) 0x40b990 MOVQ	$0,-0x40(%RCX)

(82) 0x40b998 MOVQ	$0,-0xa8(%RBX)

(82) 0x40b9a3 MOVQ	$0,-0xa0(%RBX)

(82) 0x40b9ae MOVQ	$0,-0x98(%RBX)

(82) 0x40b9b9 MOVQ	$0,-0x38(%RCX)

(82) 0x40b9c1 MOVQ	$0,-0x90(%RBX)

(82) 0x40b9cc MOVQ	$0,-0x88(%RBX)

(82) 0x40b9d7 MOVQ	$0,-0x80(%RBX)

(82) 0x40b9df MOVQ	$0,-0x30(%RCX)

(82) 0x40b9e7 MOVQ	$0,-0x78(%RBX)

(82) 0x40b9ef MOVQ	$0,-0x70(%RBX)

(82) 0x40b9f7 MOVQ	$0,-0x68(%RBX)

(82) 0x40b9ff MOVQ	$0,-0x28(%RCX)

(82) 0x40ba07 MOVQ	$0,-0x60(%RBX)

(82) 0x40ba0f MOVQ	$0,-0x58(%RBX)

(82) 0x40ba17 MOVQ	$0,-0x50(%RBX)

(82) 0x40ba1f MOVQ	$0,-0x20(%RCX)

(82) 0x40ba27 MOVQ	$0,-0x48(%RBX)

(82) 0x40ba2f MOVQ	$0,-0x40(%RBX)

(82) 0x40ba37 MOVQ	$0,-0x38(%RBX)

(82) 0x40ba3f MOVQ	$0,-0x18(%RCX)

(82) 0x40ba47 MOVQ	$0,-0x30(%RBX)

(82) 0x40ba4f MOVQ	$0,-0x28(%RBX)

(82) 0x40ba57 MOVQ	$0,-0x20(%RBX)

(82) 0x40ba5f MOVQ	$0,-0x10(%RCX)

(82) 0x40ba67 MOVQ	$0,-0x18(%RBX)

(82) 0x40ba6f MOVQ	$0,-0x10(%RBX)

(82) 0x40ba77 MOVQ	$0,-0x8(%RBX)

(82) 0x40ba7f MOVQ	$0,-0x8(%RCX)

(82) 0x40ba87 CMP	%RDX,%RCX

(82) 0x40ba8a JNE	40b968

0x40ba90 POP	%RBX

0x40ba91 POP	%R12

0x40ba93 POP	%RBP

0x40ba94 RET

0x40ba95 NOPL	(%RAX)

0x40ba98 INC	%EAX

0x40ba9a XOR	%EDX,%EDX

0x40ba9c JMP	40b7c8

0x40baa1 NOPW	%CS:(%RAX,%RAX,1)

0x40baac NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.00 to 1.18 cycles (14.46x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	103
nb uops	102
loop length	488
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.50	11.50	8.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.50	11.50	11.50	11.50	8.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	17.00
Dispatch	11.67
DIV/SQRT	6.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

2% of peak load performance is reached (2.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.00 to 11.67 cycles (1.46x speedup).

ASM code

In the binary file, the address of the function is: 40b7a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%R12),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 40ba98 <ljForce._omp_fn.0+0x2f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDX,1),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40ba90 <ljForce._omp_fn.0+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %EDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R10,2),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R8),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x28(%R8),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%RAX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R9,%R10,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R12,%R11,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b968 <ljForce._omp_fn.0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b938 <ljForce._omp_fn.0+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b911 <ljForce._omp_fn.0+0x171>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b8ea <ljForce._omp_fn.0+0x14a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b8c3 <ljForce._omp_fn.0+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b89c <ljForce._omp_fn.0+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b875 <ljForce._omp_fn.0+0xd5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40ba90 <ljForce._omp_fn.0+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40b7c8 <ljForce._omp_fn.0+0x28>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences
omp_get_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	103
nb uops	102
loop length	488
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.50	11.50	11.50	11.50	8.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.50	11.50	11.50	11.50	8.00	11.67	11.67	11.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	17.00
Dispatch	11.67
DIV/SQRT	6.00
Overall L1	17.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

2% of peak load performance is reached (2.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.18 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40b7a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 403060 <omp_get_num_threads@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 403160 <omp_get_thread_num@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x8(%R12),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CLTD
IDIV %EBX	2	2	0	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6
CMP %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JL 40ba98 <ljForce._omp_fn.0+0x2f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %ECX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RDX,1),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 40ba90 <ljForce._omp_fn.0+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %EDX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R10,2),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x20(%RDI),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%R8),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x28(%R8),%R12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R9,%RAX,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R9,%R10,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R12,%R11,8),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SUB $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b968 <ljForce._omp_fn.0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b938 <ljForce._omp_fn.0+0x198>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b911 <ljForce._omp_fn.0+0x171>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b8ea <ljForce._omp_fn.0+0x14a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b8c3 <ljForce._omp_fn.0+0x123>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b89c <ljForce._omp_fn.0+0xfc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b875 <ljForce._omp_fn.0+0xd5>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD $0x8,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40ba90 <ljForce._omp_fn.0+0x2f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40b7c8 <ljForce._omp_fn.0+0x28>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.93	0.03	0.92	0.03	0.26	0.89	0.16	1.44	0.12	1.68	0.07	1.93	0.05	2.23

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	1.11	0.38
2x2	4	0.93	1.86	2	0.62	0.4
2x4	8	0.92	3.67	4	0.34	0.39
2x8	16	0.26	2.12	8	1.05	1.21
2x16	32	0.16	2.56	16.5	0.68	1.71
2x32	64	0.12	3.79	32	0.5	1.91
2x64	128	0.07	4.78	64	0.28	2.09
2x96	192	0.05	4.78	96	0.22	2.35

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.0–	0.38	1.1
○Loop 82 - ljForce.c:161-161 - exec	0.38	1.1

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency