OV - - Function initAtoms

	Function: initAtoms	Module: exec	Source: initAtoms.c:24-50 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h: 13 - 13

--------------------------------------------------------------------------------

13:    return malloc(iSize);

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 24 - 50

--------------------------------------------------------------------------------

24: {

25:    Atoms* atoms = comdMalloc(sizeof(Atoms));

26:

27:    int maxTotalAtoms = MAXATOMS*boxes->nTotalBoxes;

28:

29:    atoms->gid =      (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

30:    atoms->iSpecies = (int*)   comdMalloc(maxTotalAtoms*sizeof(int));

31:    atoms->r =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

32:    atoms->p =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

33:    atoms->f =        (real3*) comdMalloc(maxTotalAtoms*sizeof(real3));

34:    atoms->U =        (real_t*)comdMalloc(maxTotalAtoms*sizeof(real_t));

35:

36:    atoms->nLocal = 0;

37:    atoms->nGlobal = 0;

38:

39:    for (int iOff = 0; iOff < maxTotalAtoms; iOff++)

40:    {

41:       atoms->gid[iOff] = 0;

42:       atoms->iSpecies[iOff] = 0;

43:       zeroReal3(atoms->r[iOff]);

44:       zeroReal3(atoms->p[iOff]);

45:       zeroReal3(atoms->f[iOff]);

46:       atoms->U[iOff] = 0.;

47:    }

48:

49:    return atoms;

50: }

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

0x409480 PUSH	%RBP

0x409481 MOV	%RSP,%RBP

0x409484 PUSH	%R15

0x409486 PUSH	%R14

0x409488 PUSH	%R13

0x40948a PUSH	%R12

0x40948c PUSH	%RBX

0x40948d MOV	%RDI,%RBX

0x409490 MOV	$0x38,%EDI

0x409495 SUB	$0x28,%RSP

0x409499 CALL	4030f0 <malloc@plt>

0x40949e MOV	0x14(%RBX),%R8D

0x4094a2 MOV	%RAX,%R14

0x4094a5 SAL	$0x6,%R8D

0x4094a9 MOVSXD	%R8D,%RDX

0x4094ac MOV	%R8D,-0x3c(%RBP)

0x4094b0 LEA	(,%RDX,4),%R12

0x4094b8 MOV	%RDX,-0x38(%RBP)

0x4094bc MOV	%R12,%RDI

0x4094bf CALL	4030f0 <malloc@plt>

0x4094c4 MOV	%R12,%RDI

0x4094c7 MOV	%RAX,0x8(%R14)

0x4094cb MOV	%RAX,-0x48(%RBP)

0x4094cf CALL	4030f0 <malloc@plt>

0x4094d4 MOV	%RAX,0x10(%R14)

0x4094d8 MOV	%RAX,%R15

0x4094db MOV	-0x38(%RBP),%RAX

0x4094df LEA	(%RAX,%RAX,2),%RBX

0x4094e3 SAL	$0x3,%RBX

0x4094e7 MOV	%RBX,%RDI

0x4094ea CALL	4030f0 <malloc@plt>

0x4094ef MOV	%RBX,%RDI

0x4094f2 MOV	%RAX,0x18(%R14)

0x4094f6 MOV	%RAX,%R13

0x4094f9 CALL	4030f0 <malloc@plt>

0x4094fe MOV	%RBX,%RDI

0x409501 MOV	%RAX,0x20(%R14)

0x409505 MOV	%RAX,%R12

0x409508 CALL	4030f0 <malloc@plt>

0x40950d MOV	-0x38(%RBP),%RCX

0x409511 MOV	%RAX,0x28(%R14)

0x409515 MOV	%RAX,%RBX

0x409518 LEA	(,%RCX,8),%RDI

0x409520 CALL	4030f0 <malloc@plt>

0x409525 MOV	-0x3c(%RBP),%R10D

0x409529 MOVQ	$0,(%R14)

0x409530 MOV	%RAX,0x30(%R14)

0x409534 TEST	%R10D,%R10D

0x409537 JLE	409867

0x40953d MOV	%R10D,%ESI

0x409540 XOR	%EDX,%EDX

0x409542 XOR	%R8D,%R8D

0x409545 MOV	-0x48(%RBP),%R11

0x409549 AND	$0x3,%ESI

0x40954c MOV	%RAX,%RDI

0x40954f JE	4096a8

0x409555 MOV	$0x1,%R8D

0x40955b MOV	$0x18,%EDX

0x409560 MOVL	$0,(%R11)

0x409567 MOVL	$0,(%R15)

0x40956e MOVL	$0,(%R11,%R8,4)

0x409576 MOVL	$0,(%R15,%R8,4)

0x40957e MOVQ	$0,(%RAX)

0x409585 MOVQ	$0,(%RAX,%R8,8)

0x40958d INC	%R8

0x409590 MOVQ	$0,(%R13)

0x409598 MOVQ	$0,0x8(%R13)

0x4095a0 MOVQ	$0,0x10(%R13)

0x4095a8 MOVQ	$0,(%R12)

0x4095b0 MOVQ	$0,0x8(%R12)

0x4095b9 MOVQ	$0,0x10(%R12)

0x4095c2 MOVQ	$0,(%RBX)

0x4095c9 MOVQ	$0,0x8(%RBX)

0x4095d1 MOVQ	$0,0x10(%RBX)

0x4095d9 MOVQ	$0,(%R13,%RDX,1)

0x4095e2 MOVQ	$0,0x8(%R13,%RDX,1)

0x4095eb MOVQ	$0,0x10(%R13,%RDX,1)

0x4095f4 MOVQ	$0,(%R12,%RDX,1)

0x4095fc MOVQ	$0,0x8(%R12,%RDX,1)

0x409605 MOVQ	$0,0x10(%R12,%RDX,1)

0x40960e MOVQ	$0,(%RBX,%RDX,1)

0x409616 MOVQ	$0,0x8(%RBX,%RDX,1)

0x40961f MOVQ	$0,0x10(%RBX,%RDX,1)

0x409628 MOVL	$0,(%R11,%R8,4)

0x409630 MOVL	$0,(%R15,%R8,4)

0x409638 MOVQ	$0,0x18(%R13,%RDX,1)

0x409641 MOVQ	$0,0x20(%R13,%RDX,1)

0x40964a MOVQ	$0,0x28(%R13,%RDX,1)

0x409653 MOVQ	$0,0x18(%R12,%RDX,1)

0x40965c MOVQ	$0,0x20(%R12,%RDX,1)

0x409665 MOVQ	$0,0x28(%R12,%RDX,1)

0x40966e MOVQ	$0,0x18(%RBX,%RDX,1)

0x409677 MOVQ	$0,(%RAX,%R8,8)

0x40967f INC	%R8

0x409682 MOVQ	$0,0x20(%RBX,%RDX,1)

0x40968b MOVQ	$0,0x28(%RBX,%RDX,1)

0x409694 ADD	$0x30,%RDX

0x409698 CMP	%R8D,%R10D

0x40969b JLE	409867

0x4096a1 NOPL	(%RAX)

(66) 0x4096a8 MOVL	$0,(%R11,%R8,4)

(66) 0x4096b0 LEA	0x1(%R8),%R9

(66) 0x4096b4 LEA	0x2(%R8),%RAX

(66) 0x4096b8 MOVL	$0,(%R15,%R8,4)

(66) 0x4096c0 LEA	0x3(%R8),%RCX

(66) 0x4096c4 MOVQ	$0,(%RDI,%R8,8)

(66) 0x4096cc ADD	$0x4,%R8

(66) 0x4096d0 MOVQ	$0,(%R13,%RDX,1)

(66) 0x4096d9 MOVQ	$0,0x8(%R13,%RDX,1)

(66) 0x4096e2 MOVQ	$0,0x10(%R13,%RDX,1)

(66) 0x4096eb MOVQ	$0,(%R12,%RDX,1)

(66) 0x4096f3 MOVQ	$0,0x8(%R12,%RDX,1)

(66) 0x4096fc MOVQ	$0,0x10(%R12,%RDX,1)

(66) 0x409705 MOVQ	$0,(%RBX,%RDX,1)

(66) 0x40970d MOVQ	$0,0x8(%RBX,%RDX,1)

(66) 0x409716 MOVQ	$0,0x10(%RBX,%RDX,1)

(66) 0x40971f MOVL	$0,(%R11,%R9,4)

(66) 0x409727 MOVL	$0,(%R15,%R9,4)

(66) 0x40972f MOVQ	$0,0x18(%R13,%RDX,1)

(66) 0x409738 MOVQ	$0,0x20(%R13,%RDX,1)

(66) 0x409741 MOVQ	$0,0x28(%R13,%RDX,1)

(66) 0x40974a MOVQ	$0,0x18(%R12,%RDX,1)

(66) 0x409753 MOVQ	$0,0x20(%R12,%RDX,1)

(66) 0x40975c MOVQ	$0,0x28(%R12,%RDX,1)

(66) 0x409765 MOVQ	$0,0x18(%RBX,%RDX,1)

(66) 0x40976e MOVQ	$0,0x20(%RBX,%RDX,1)

(66) 0x409777 MOVQ	$0,0x28(%RBX,%RDX,1)

(66) 0x409780 MOVQ	$0,0x30(%R13,%RDX,1)

(66) 0x409789 MOVQ	$0,0x38(%R13,%RDX,1)

(66) 0x409792 MOVQ	$0,0x40(%R13,%RDX,1)

(66) 0x40979b MOVQ	$0,0x30(%R12,%RDX,1)

(66) 0x4097a4 MOVQ	$0,0x38(%R12,%RDX,1)

(66) 0x4097ad MOVQ	$0,0x40(%R12,%RDX,1)

(66) 0x4097b6 MOVQ	$0,(%RDI,%R9,8)

(66) 0x4097be MOVL	$0,(%R11,%RAX,4)

(66) 0x4097c6 MOVL	$0,(%R15,%RAX,4)

(66) 0x4097ce MOVQ	$0,0x30(%RBX,%RDX,1)

(66) 0x4097d7 MOVQ	$0,0x38(%RBX,%RDX,1)

(66) 0x4097e0 MOVQ	$0,0x40(%RBX,%RDX,1)

(66) 0x4097e9 MOVQ	$0,(%RDI,%RAX,8)

(66) 0x4097f1 MOVQ	$0,0x48(%R13,%RDX,1)

(66) 0x4097fa MOVQ	$0,0x50(%R13,%RDX,1)

(66) 0x409803 MOVQ	$0,0x58(%R13,%RDX,1)

(66) 0x40980c MOVQ	$0,0x48(%R12,%RDX,1)

(66) 0x409815 MOVQ	$0,0x50(%R12,%RDX,1)

(66) 0x40981e MOVQ	$0,0x58(%R12,%RDX,1)

(66) 0x409827 MOVQ	$0,0x48(%RBX,%RDX,1)

(66) 0x409830 MOVQ	$0,0x50(%RBX,%RDX,1)

(66) 0x409839 MOVQ	$0,0x58(%RBX,%RDX,1)

(66) 0x409842 ADD	$0x60,%RDX

(66) 0x409846 MOVL	$0,(%R11,%RCX,4)

(66) 0x40984e MOVL	$0,(%R15,%RCX,4)

(66) 0x409856 MOVQ	$0,(%RDI,%RCX,8)

(66) 0x40985e CMP	%R8D,%R10D

(66) 0x409861 JG	4096a8

0x409867 ADD	$0x28,%RSP

0x40986b MOV	%R14,%RAX

0x40986e POP	%RBX

0x40986f POP	%R12

0x409871 POP	%R13

0x409873 POP	%R14

0x409875 POP	%R15

0x409877 POP	%RBP

0x409878 RET

0x409879 NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 19.33 to 1.60 cycles (12.05x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

malloc@plt: 7 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 340 bytes.

General properties

nb instructions	110
nb uops	115
loop length	577
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.50	5.50	5.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.50	5.50	5.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.17
Dispatch	19.33
Overall L1	19.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.33 cycles. At this rate:

1% of peak load performance is reached (1.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (17.59 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 409480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV $0x38,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x14(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R8D	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOVSXD %R8D,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8D,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA (,%RDX,4),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RAX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RAX,%RAX,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x20(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,0x28(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
LEA (,%RCX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV -0x3c(%RBP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVQ $0,(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,0x30(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 409867 <initAtoms+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R10D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
AND $0x3,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
JE 4096a8 <initAtoms+0x228>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x18,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVL $0,(%R11)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R11,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R11,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x20(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x20(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,0x20(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
ADD $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %R8D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 409867 <initAtoms+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0.17
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	initAtoms.c:24-50
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/memUtils.h:13
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:24-50
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

malloc@plt: 7 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 340 bytes.

General properties

nb instructions	110
nb uops	115
loop length	577
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.50	5.50	5.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.50	5.50	5.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.17
Dispatch	19.33
Overall L1	19.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.33 cycles. At this rate:

1% of peak load performance is reached (1.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (17.59 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 409480

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV $0x38,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x14(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R8D	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOVSXD %R8D,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8D,-0x3c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA (,%RDX,4),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RAX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%RAX,%RAX,2),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SAL $0x3,%RBX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,0x20(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RAX,0x28(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
LEA (,%RCX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030f0 <malloc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV -0x3c(%RBP),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVQ $0,(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,0x30(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 409867 <initAtoms+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R10D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
AND $0x3,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
JE 4096a8 <initAtoms+0x228>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV $0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x18,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVL $0,(%R11)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R11,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R12)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x8(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x10(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R11,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,(%R15,%R8,4)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x20(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%R13,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x20(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%R12,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x18(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,(%RAX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,0x20(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,0x28(%RBX,%RDX,1)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
ADD $0x30,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %R8D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 409867 <initAtoms+0x3e7>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x28,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0.17
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.5	-0	0.75	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.01
2x2	2	1.5	3	2	0.01	0
2x4	2	0.75	3	4	0.03	0.01
2x8	2	1	1	8	0.03	0.01
2x16	2	1	1	16.5	0.04	0.01
2x32	2	1	1	32	0.01	0
2x64	2	1	1	64	0.02	0
2x96	2	1	1	96	0.02	0

Name	Coverage (%)	Time (s)
▼initAtoms–	0.01	0.03
○Loop 66 - initAtoms.c:39-46 - exec	0.01	0.03

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency