OV - - Function unloadAtomsBuffer

	Function: unloadAtomsBuffer	Module: exec	Source: haloExchange.c:407-426 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 407 - 426

--------------------------------------------------------------------------------

407: {

408:    AtomExchangeParms* parms = (AtomExchangeParms*) vparms;

409:    SimFlat* s = (SimFlat*) data;

410:    AtomMsg* buf = (AtomMsg*) charBuf;

411:    int nBuf = bufSize / sizeof(AtomMsg);

412:    assert(bufSize % sizeof(AtomMsg) == 0);

413:

414:    for (int ii=0; ii<nBuf; ++ii)

[...]

424:       putAtomInBox(s->boxes, s->atoms, gid, type, rx, ry, rz, px, py, pz);

425:    }

426: }

0x4077f0 MOV	$0x2492492492492493,%RAX

0x4077fa MOVSXD	%ECX,%RCX

0x4077fd PUSH	%RBP

0x4077fe MOV	%RCX,%RDX

0x407801 SHR	$0x3,%RDX

0x407805 MUL	%RDX

0x407808 MOV	%RSP,%RBP

0x40780b PUSH	%R14

0x40780d PUSH	%R13

0x40780f PUSH	%R12

0x407811 MOV	%RSI,%R12

0x407814 PUSH	%RBX

0x407815 IMUL	$0x38,%RDX,%RBX

0x407819 CMP	%RBX,%RCX

0x40781c JNE	407908

0x407822 TEST	%EDX,%EDX

0x407824 JLE	4078ff

0x40782a LEA	-0x1(%RDX),%R13D

0x40782e LEA	0x38(%R8),%R14

0x407832 MOV	%R8,%RBX

0x407835 IMUL	$0x38,%R13,%R13

0x407839 ADD	%R14,%R13

0x40783c MOV	%R13,%RSI

0x40783f SUB	%R8,%RSI

0x407842 TEST	$0x8,%SIL

0x407846 JE	407890

0x407848 VMOVSD	0x8(%R8),%XMM0

0x40784e MOV	0x4(%R8),%ECX

0x407852 MOV	%R14,%RBX

0x407855 MOV	(%R8),%EDX

0x407858 MOV	0x20(%R12),%RSI

0x40785d MOV	0x18(%R12),%RDI

0x407862 VMOVSD	0x30(%R8),%XMM5

0x407868 VMOVSD	0x28(%R8),%XMM4

0x40786e VMOVSD	0x20(%R8),%XMM3

0x407874 VMOVSD	0x18(%R8),%XMM2

0x40787a VMOVSD	0x10(%R8),%XMM1

0x407880 CALL	40ae60 <putAtomInBox>

0x407885 CMP	%R13,%R14

0x407888 JE	4078ff

0x40788a NOPW	(%RAX,%RAX,1)

(40) 0x407890 VMOVSD	0x8(%RBX),%XMM0

(40) 0x407895 MOV	0x4(%RBX),%ECX

(40) 0x407898 ADD	$0x70,%RBX

(40) 0x40789c MOV	-0x70(%RBX),%EDX

(40) 0x40789f VMOVSD	-0x40(%RBX),%XMM5

(40) 0x4078a4 VMOVSD	-0x48(%RBX),%XMM4

(40) 0x4078a9 VMOVSD	-0x50(%RBX),%XMM3

(40) 0x4078ae VMOVSD	-0x58(%RBX),%XMM2

(40) 0x4078b3 VMOVSD	-0x60(%RBX),%XMM1

(40) 0x4078b8 MOV	0x20(%R12),%RSI

(40) 0x4078bd MOV	0x18(%R12),%RDI

(40) 0x4078c2 CALL	40ae60 <putAtomInBox>

(40) 0x4078c7 VMOVSD	-0x30(%RBX),%XMM0

(40) 0x4078cc MOV	-0x34(%RBX),%ECX

(40) 0x4078cf MOV	-0x38(%RBX),%EDX

(40) 0x4078d2 VMOVSD	-0x8(%RBX),%XMM5

(40) 0x4078d7 VMOVSD	-0x10(%RBX),%XMM4

(40) 0x4078dc VMOVSD	-0x18(%RBX),%XMM3

(40) 0x4078e1 VMOVSD	-0x20(%RBX),%XMM2

(40) 0x4078e6 VMOVSD	-0x28(%RBX),%XMM1

(40) 0x4078eb MOV	0x20(%R12),%RSI

(40) 0x4078f0 MOV	0x18(%R12),%RDI

(40) 0x4078f5 CALL	40ae60 <putAtomInBox>

(40) 0x4078fa CMP	%R13,%RBX

(40) 0x4078fd JNE	407890

0x4078ff POP	%RBX

0x407900 POP	%R12

0x407902 POP	%R13

0x407904 POP	%R14

0x407906 POP	%RBP

0x407907 RET

0x407908 MOV	$0x411cf0,%ECX

0x40790d MOV	$0x19c,%EDX

0x407912 MOV	$0x411b10,%ESI

0x407917 MOV	$0x411bc8,%EDI

0x40791c CALL	4030c0 <__assert_fail@plt>

0x407921 NOPW	%CS:(%RAX,%RAX,1)

0x40792c NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	haloExchange.c:407-426
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:407-414,424-426.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 2.83 cycles (3.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 0.79 cycles (11.37x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences
putAtomInBox: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes.

General properties

nb instructions	54
nb uops	54
loop length	209
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.50	5.50	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.50	5.50	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	5.75
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 5.75 cycles (1.57x speedup).

ASM code

In the binary file, the address of the function is: 4077f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV $0x2492492492492493,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MUL %RDX	2	0	2	0	0	0	0	0	0	3-4	1
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
IMUL $0x38,%RDX,%RBX	1	0	1	0	0	0	0	0	0	3	1
CMP %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JNE 407908 <unloadAtomsBuffer+0x118>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4078ff <unloadAtomsBuffer+0x10f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
LEA -0x1(%RDX),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x38(%R8),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
IMUL $0x38,%R13,%R13	1	0	1	0	0	0	0	0	0	3	1
ADD %R14,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
SUB %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
TEST $0x8,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 407890 <unloadAtomsBuffer+0xa0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
VMOVSD 0x8(%R8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
MOV 0x4(%R8),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%R8),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R12),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVSD 0x30(%R8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x28(%R8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x20(%R8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x18(%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x10(%R8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
CALL 40ae60 <putAtomInBox>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
CMP %R13,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 4078ff <unloadAtomsBuffer+0x10f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV $0x411cf0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x19c,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411b10,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411bc8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	haloExchange.c:407-426
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:407-414,424-426.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 2.83 cycles (3.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences
putAtomInBox: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes.

General properties

nb instructions	54
nb uops	54
loop length	209
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.50	5.50	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.50	5.50	3.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.00
Dispatch	5.75
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4077f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV $0x2492492492492493,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MUL %RDX	2	0	2	0	0	0	0	0	0	3-4	1
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
IMUL $0x38,%RDX,%RBX	1	0	1	0	0	0	0	0	0	3	1
CMP %RBX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JNE 407908 <unloadAtomsBuffer+0x118>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4078ff <unloadAtomsBuffer+0x10f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
LEA -0x1(%RDX),%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x38(%R8),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
IMUL $0x38,%R13,%R13	1	0	1	0	0	0	0	0	0	3	1
ADD %R14,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
SUB %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
TEST $0x8,%SIL	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 407890 <unloadAtomsBuffer+0xa0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
VMOVSD 0x8(%R8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
MOV 0x4(%R8),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%R8),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R12),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%R12),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVSD 0x30(%R8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x28(%R8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x20(%R8),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x18(%R8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
VMOVSD 0x10(%R8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	1	0.50
CALL 40ae60 <putAtomInBox>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
CMP %R13,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JE 4078ff <unloadAtomsBuffer+0x10f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV $0x411cf0,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x19c,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411b10,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x411bc8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4030c0 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	0.5	0.01	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.04	0.01
2x2	2	1	2	2	0.01	0
2x4	2	0.5	2	4	0.03	0.01
2x8	2	1	1	8	0.02	0
2x16	2	1	1	16.5	0.04	0.01
2x32	2	1	1	32	0.03	0.01
2x64	2	1	1	64	0.03	0.01
2x96	2	1	1	96	0.04	0

Name	Coverage (%)	Time (s)
▼unloadAtomsBuffer–	0.01	0.02
○Loop 40 - haloExchange.c:414-424 - exec	0.01	0.02

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency