OV - exec - Loop 92

	Loop Id: 92	Module: exec	Source: initAtoms.c:177-181	Coverage: 0.01%

0x20d520 VMOVUPD	(%R13),%ZMM18    [1]

0x20d527 VMOVUPD	0x40(%R13),%ZMM19    [1]

0x20d52e VMOVUPD	0x80(%R13),%ZMM20    [1]

0x20d535 VBROADCASTSD	(%RBX),%ZMM17    [2]

0x20d53b VMOVAPD	%ZMM18,%ZMM21

0x20d541 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

0x20d547 VMOVAPD	%ZMM18,%ZMM22

0x20d54d VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

0x20d553 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

0x20d559 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

0x20d55f VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

0x20d565 VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

0x20d56b VMULPD	%ZMM21,%ZMM17,%ZMM18

0x20d571 VMULPD	%ZMM22,%ZMM17,%ZMM20

0x20d577 VMULPD	%ZMM19,%ZMM17,%ZMM17

0x20d57d VMOVAPD	%ZMM20,%ZMM19

0x20d583 VPERMT2PD	%ZMM18,%ZMM11,%ZMM19

0x20d589 VMOVAPD	%ZMM18,%ZMM21

0x20d58f VPERMT2PD	%ZMM20,%ZMM13,%ZMM21

0x20d595 VPERMT2PD	%ZMM20,%ZMM15,%ZMM18

0x20d59b VPERMT2PD	%ZMM17,%ZMM12,%ZMM19

0x20d5a1 VPERMT2PD	%ZMM17,%ZMM14,%ZMM21

0x20d5a7 VPERMT2PD	%ZMM17,%ZMM16,%ZMM18

0x20d5ad VMOVUPD	%ZMM18,(%R13)    [1]

0x20d5b4 VMOVUPD	%ZMM21,0x40(%R13)    [1]

0x20d5bb VMOVUPD	%ZMM19,0x80(%R13)    [1]

0x20d5c2 ADD	$0xc0,%R13

0x20d5c9 ADD	$-0x8,%R14

0x20d5cd JNE	20d520

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 177 - 181

--------------------------------------------------------------------------------

177:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

178:       {

179:          s->atoms->p[iOff][0] *= scaleFactor;

180:          s->atoms->p[iOff][1] *= scaleFactor;

181:          s->atoms->p[iOff][2] *= scaleFactor;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.08
Bottlenecks	P9, P10,
Function	.omp_outlined..7
Source	initAtoms.c:177-181
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	12.06
Front-end cycles	5.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	6.00
P8 cycles	12.50
P9 cycles	12.50
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	31.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.92
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.36
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	96.15
Vectorization ratio load	75.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.12
Vector-efficiency ratio all	96.63
Vector-efficiency ratio load	78.13
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	94.85

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.08
Bottlenecks	P9, P10,
Function	.omp_outlined..7
Source	initAtoms.c:177-181
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	12.06
Front-end cycles	5.17
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	6.00
P8 cycles	12.50
P9 cycles	12.50
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	31.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.92
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.36
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	96.15
Vectorization ratio load	75.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	94.12
Vector-efficiency ratio all	96.63
Vector-efficiency ratio load	78.13
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	94.85

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..7
Source file and lines	initAtoms.c:177-181
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:177-181.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.50 to 12.06 cycles (1.04x speedup).

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 6.00 cycles (2.08x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: multiply

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	31
loop length	179
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	18
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.33	2.33	2.33	3.00	12.50	12.50	0.00	3.00	3.00
cycles	0.50	0.50	0.25	0.25	0.50	3.33	3.33	3.33	6.00	12.50	12.50	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.17
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	96%
load	75%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

all	96%
load	78%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (15.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d520

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R13),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R13),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R13),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMULPD %ZMM21,%ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMULPD %ZMM22,%ZMM17,%ZMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMULPD %ZMM19,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMOVAPD %ZMM20,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM18,%ZMM11,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM13,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM15,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM12,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM14,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM16,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM18,(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM21,0x40(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM19,0x80(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
ADD $0xc0,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 20d520 <.omp_outlined..7+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined..7
Source file and lines	initAtoms.c:177-181
Module	exec

gain
potential
hint
expert

Vectorization

Details

96% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: multiply

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	31
loop length	179
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	18
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.33	2.33	2.33	3.00	12.50	12.50	0.00	3.00	3.00
cycles	0.50	0.50	0.25	0.25	0.50	3.33	3.33	3.33	6.00	12.50	12.50	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.17
Dispatch	12.50
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

all	96%
load	75%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

all	96%
load	78%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (15.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d520

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R13),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R13),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R13),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMULPD %ZMM21,%ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMULPD %ZMM22,%ZMM17,%ZMM20	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMULPD %ZMM19,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	1
VMOVAPD %ZMM20,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM18,%ZMM11,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM13,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM15,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM12,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM14,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM17,%ZMM16,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM18,(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM21,0x40(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM19,0x80(%R13)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
ADD $0xc0,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 20d520 <.omp_outlined..7+0x220>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

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Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code