OV - exec - Loop 87

	Loop Id: 87	Module: exec	Source: ljForce.c:191-216 [...]	Coverage: 30.11%

0x20f180 INC	%R11

0x20f183 ADD	$0x18,%R10

0x20f187 CMP	%R13,%R11

0x20f18a JGE	20f160

0x20f18c VMOVUPD	(%R9),%XMM7    [10]

0x20f191 VSUBPD	-0x10(%R10),%XMM7,%XMM7    [5]

0x20f197 VMOVAPD	%XMM7,%XMM8

0x20f19b VFMADD213SD	%XMM0,%XMM7,%XMM8

0x20f1a0 VPERMILPD	$0x1,%XMM7,%XMM9

0x20f1a6 VFMADD213SD	%XMM8,%XMM9,%XMM9

0x20f1ab VMOVSD	0x10(%R9),%XMM8    [10]

0x20f1b1 VSUBSD	(%R10),%XMM8,%XMM8    [5]

0x20f1b6 VFMADD231SD	%XMM8,%XMM8,%XMM9

0x20f1bb VUCOMISD	%XMM0,%XMM9

0x20f1bf JBE	20f180

0x20f1c1 VMOVSD	(%R15),%XMM10    [2]

0x20f1c6 VUCOMISD	%XMM9,%XMM10

0x20f1cb JB	20f180

0x20f1cd VDIVSD	%XMM9,%XMM1,%XMM9

0x20f1d2 MOV	0x30(%RSI),%RBX    [1]

0x20f1d6 VMOVSD	(%RBX,%RAX,8),%XMM12    [8]

0x20f1db VMULSD	%XMM9,%XMM9,%XMM10

0x20f1e0 VMULSD	%XMM10,%XMM9,%XMM10

0x20f1e5 VMULSD	(%R14),%XMM10,%XMM10    [3]

0x20f1ea VADDSD	%XMM2,%XMM10,%XMM11

0x20f1ee VFMSUB213SD	(%RDX),%XMM10,%XMM11    [6]

0x20f1f3 VFMADD231SD	%XMM3,%XMM11,%XMM12

0x20f1f8 VMOVSD	%XMM12,(%RBX,%RAX,8)    [8]

0x20f1fd VFMADD213SD	-0x38(%RBP),%XMM3,%XMM11    [9]

0x20f203 VMOVSD	%XMM11,-0x38(%RBP)    [9]

0x20f208 VMULSD	(%RCX),%XMM4,%XMM11    [4]

0x20f20c MOV	0x28(%RSI),%RBX    [1]

0x20f210 VMULSD	%XMM11,%XMM10,%XMM11

0x20f215 VFMADD213SD	%XMM6,%XMM5,%XMM10

0x20f21a VMULSD	%XMM11,%XMM9,%XMM9

0x20f21f VMULSD	%XMM9,%XMM10,%XMM9

0x20f224 VMOVDDUP	%XMM9,%XMM10

0x20f229 VFNMADD213PD	(%RBX,%R12,8),%XMM7,%XMM10    [7]

0x20f22f VMOVUPD	%XMM10,(%RBX,%R12,8)    [7]

0x20f235 VFNMADD213SD	0x10(%RBX,%R12,8),%XMM9,%XMM8    [7]

0x20f23c VMOVSD	%XMM8,0x10(%RBX,%R12,8)    [7]

0x20f243 JMP	20f180

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216

--------------------------------------------------------------------------------

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	1.02
CQA speedup if FP arith vectorized	1.71
CQA speedup if fully vectorized	4.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	4.83
CQA cycles if no scalar integer	4.72
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	1.12
Front-end cycles	4.44
DIV/SQRT cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.83
P8 cycles	4.17
P9 cycles	2.56
P10 cycles	2.44
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.67
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	26.67
Nb loads	7.67
Nb stores	1.33
Nb stack references	0.33
FLOP/cycle	3.45
Nb FLOP add-sub	3.33
Nb FLOP mul	2.33
Nb FLOP fma	5.33
Nb FLOP div	0.33
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.50
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	13.33
Stride 0	3.33
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.67
Vectorization ratio all	30.51
Vectorization ratio load	38.33
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	44.44
Vectorization ratio fma	3.70
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	52.22
Vector-efficiency ratio all	16.31
Vector-efficiency ratio load	17.29
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	18.06
Vector-efficiency ratio fma	12.96
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.03

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	5.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	micro-operation queue,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	2.67
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.33
CQA cycles if fully vectorized	0.52
Front-end cycles	2.67
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.50
P8 cycles	1.83
P9 cycles	1.83
P10 cycles	1.83
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	16.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.37
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	40.00
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	66.67
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	3.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	P8, P9,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	2.25
Front-end cycles	7.33
DIV/SQRT cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	2.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	3.50
P10 cycles	3.50
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	44.00
Nb loads	14.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	3.76
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.71
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	40.00
Stride 0	7.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	18.18
Vectorization ratio load	25.00
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	11.11
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	40.00
Vector-efficiency ratio all	14.77
Vector-efficiency ratio load	15.63
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	16.67
Vector-efficiency ratio fma	13.89
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.50

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	5.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	micro-operation queue,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	3.33
CQA cycles if no scalar integer	3.17
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.58
Front-end cycles	3.33
DIV/SQRT cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.50
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	1.67
P7 cycles	1.50
P8 cycles	2.17
P9 cycles	2.33
P10 cycles	2.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	20.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.70
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	40.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:191-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

It is main loop of related source loop which is unrolled by 12 (including vectorization).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.83 to 1.12 cycles (4.32x speedup).

Details

30% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

38% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
44% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
3% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
52% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 5.33 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1.67 occurrences

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16.666666666667 FP arithmetical operations:

8.67: addition or subtraction (5 inside FMA instructions)
7.67: multiply (5 inside FMA instructions)
0.33: divide

The binary loop is loading 80 bytes (10 double precision FP elements). The binary loop is storing 13 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	26.67
loop length	114
used x86 registers	7.33
used mmx registers	0
used xmm registers	7.33
used ymm registers	0
used zmm registers	0
nb stack references	0.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.44 cycles
front end	4.44 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.00	1.00	1.00	1.50	3.00	3.00	3.00	3.83	4.17	2.56	2.44	1.50	1.50
cycles	1.50	1.00	1.00	1.00	1.50	3.00	3.00	3.00	3.83	4.17	2.56	2.44	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	1.67
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.44
Dispatch	4.22
DIV/SQRT	1.67
Data deps.	1.00
Overall L1	4.83

Vectorization ratios

all	30%
load	38%
store	25%
mul	0%
add-sub	44%
fma	3%
div/sqrt	0%
other	52%

Vector efficiency ratios

all	16%
load	17%
store	15%
mul	12%
add-sub	18%
fma	12%
div/sqrt	12%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

17% of peak load performance is reached (16.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.57 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.67 to 2.50 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.67 to 0.52 cycles (5.12x speedup).

Details

40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	15
nb uops	16
loop length	65
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.67 cycles
front end	2.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.83	1.83	1.83	0.50	0.50
cycles	1.00	1.00	1.00	1.00	1.00	1.33	1.33	1.33	1.50	1.83	1.83	1.83	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.67
Dispatch	1.83
Data deps.	1.00
Overall L1	2.67

Vectorization ratios

all	40%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

Vector efficiency ratios

all	17%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.67 to 1.83 cycles (1.45x speedup).

ASM code

In the binary file, the address of the loop is: 20f18c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 20f160 <.omp_outlined..5+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD (%R9),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VSUBPD -0x10(%R10),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213SD %XMM0,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPERMILPD $0x1,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD213SD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x10(%R9),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R10),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VFMADD231SD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VUCOMISD %XMM0,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 8.50 to 2.25 cycles (3.78x speedup).

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
11% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 7.33 cycles (1.16x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

14: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop is loading 136 bytes (17 double precision FP elements). The binary loop is storing 40 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	42
nb uops	44
loop length	200
used x86 registers	13
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	0.43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.33 cycles
front end	7.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.00	1.00	1.00	2.00	6.00	6.00	6.00	8.50	8.50	3.50	3.50	3.00	3.00
cycles	2.00	1.00	1.00	1.00	2.00	6.00	6.00	6.00	8.50	8.50	3.50	3.50	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.33
Dispatch	8.50
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	18%
load	25%
store	25%
mul	0%
add-sub	33%
fma	11%
div/sqrt	0%
other	40%

Vector efficiency ratios

all	14%
load	15%
store	15%
mul	12%
add-sub	16%
fma	13%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f18c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 20f160 <.omp_outlined..5+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD (%R9),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VSUBPD -0x10(%R10),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213SD %XMM0,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPERMILPD $0x1,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD213SD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x10(%R9),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R10),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VFMADD231SD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VUCOMISD %XMM0,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%R15),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM9,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VDIVSD %XMM9,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOV 0x30(%RSI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD (%RBX,%RAX,8),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULSD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD (%R14),%XMM10,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VADDSD %XMM2,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VFMSUB213SD (%RDX),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM3,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM12,(%RBX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VFMADD213SD -0x38(%RBP),%XMM3,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM11,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMULSD (%RCX),%XMM4,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOV 0x28(%RSI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD %XMM11,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD213SD %XMM6,%XMM5,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMULSD %XMM11,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULSD %XMM9,%XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVDDUP %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFNMADD213PD (%RBX,%R12,8),%XMM7,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVUPD %XMM10,(%RBX,%R12,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VFNMADD213SD 0x10(%RBX,%R12,8),%XMM9,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD %XMM8,0x10(%RBX,%R12,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
JMP 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 3.17 cycles (1.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

6: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)

The binary loop is loading 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	20
loop length	77
used x86 registers	5
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	1.00	1.00	1.00	1.50	1.67	1.67	1.67	1.50	2.17	2.33	2.00	1.00	1.00
cycles	1.50	1.00	1.00	1.00	1.50	1.67	1.67	1.67	1.50	2.17	2.33	2.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.33
Dispatch	2.33
Data deps.	1.00
Overall L1	3.33

Vectorization ratios

all	33%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	16%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

17% of peak load performance is reached (16.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 20f18c

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x18,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JGE 20f160 <.omp_outlined..5+0x290>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD (%R9),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VSUBPD -0x10(%R10),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVAPD %XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213SD %XMM0,%XMM7,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPERMILPD $0x1,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD213SD %XMM8,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x10(%R9),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VSUBSD (%R10),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VFMADD231SD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VUCOMISD %XMM0,%XMM9	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JBE 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%R15),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM9,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
JB 20f180 <.omp_outlined..5+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set