OV - exec - Loop 83

	Loop Id: 83	Module: exec	Source: ljForce.c:173-216 [...]	Coverage: 0.02%

0x20f080 MOV	-0x60(%RBP),%RSI

0x20f084 ADDL	$0x40,-0x3c(%RBP)

0x20f088 LEA	0x1(%RSI),%RAX

0x20f08c CMP	%RSI,-0x80(%RBP)

0x20f090 JLE	20ef6e

0x20f096 CMPL	$0,-0x48(%RBP)

0x20f09a MOV	%RAX,-0x60(%RBP)

0x20f09e JLE	20f080

0x20f0a0 MOV	-0x78(%RBP),%RSI

0x20f0a4 MOV	-0x60(%RBP),%RDI

0x20f0a8 MOV	-0x68(%RBP),%RAX

0x20f0ac MOV	0x80(%RSI),%RSI

0x20f0b3 MOV	(%RAX,%RDI,4),%EAX

0x20f0b6 MOV	(%RSI,%RDI,8),%RSI

0x20f0ba MOV	%RSI,-0x70(%RBP)

0x20f0be TEST	%EAX,%EAX

0x20f0c0 JLE	20f250

0x20f0c6 MOVSXD	-0x3c(%RBP),%RSI

0x20f0ca MOV	%RSI,-0x90(%RBP)

0x20f0d1 MOV	%EDI,%ESI

0x20f0d3 SAL	$0x6,%ESI

0x20f0d6 ADD	%ESI,%EAX

0x20f0d8 XOR	%ESI,%ESI

0x20f0da CLTQ

0x20f0dc MOV	%RAX,-0xa0(%RBP)

0x20f0e3 JMP	20f100

  (85) 0x20f0f0 MOV	-0x98(%RBP),%RSI

  (85) 0x20f0f7 INC	%RSI

  (85) 0x20f0fa CMP	%RSI,-0x48(%RBP)

  (85) 0x20f0fe JE	20f080

  (85) 0x20f100 MOV	-0x70(%RBP),%RAX

  (85) 0x20f104 MOV	(%RAX,%RSI,4),%EAX

  (85) 0x20f107 TEST	%EAX,%EAX

  (85) 0x20f109 JS	20f2bc

  (85) 0x20f10f MOV	%RSI,-0x98(%RBP)

  (85) 0x20f116 MOV	-0x68(%RBP),%RSI

  (85) 0x20f11a MOV	(%RSI,%RAX,4),%ESI

  (85) 0x20f11d TEST	%ESI,%ESI

  (85) 0x20f11f JLE	20f0f0

  (85) 0x20f121 SAL	$0x6,%EAX

  (85) 0x20f124 ADD	%EAX,%ESI

  (85) 0x20f126 MOVSXD	%EAX,%RDI

  (85) 0x20f129 MOVSXD	%ESI,%R13

  (85) 0x20f12c MOV	-0x88(%RBP),%RSI

  (85) 0x20f133 LEA	(%RDI,%RDI,2),%RAX

  (85) 0x20f137 MOV	0x20(%RSI),%RSI

  (85) 0x20f13b MOV	0x18(%RSI),%R8

  (85) 0x20f13f LEA	0x10(%R8,%RAX,8),%RAX

  (85) 0x20f144 MOV	%RAX,-0xa8(%RBP)

  (85) 0x20f14b MOV	-0x90(%RBP),%RAX

  (85) 0x20f152 JMP	20f16c

    (86) 0x20f160 INC	%RAX

    (86) 0x20f163 CMP	%RAX,-0xa0(%RBP)

    (86) 0x20f16a JLE	20f0f0

    (86) 0x20f16c MOV	-0xa8(%RBP),%R10

    (86) 0x20f173 LEA	(%RAX,%RAX,2),%R12

    (86) 0x20f177 MOV	%RDI,%R11

    (86) 0x20f17a LEA	(%R8,%R12,8),%R9

    (86) 0x20f17e JMP	20f18c

      (87) 0x20f180 INC	%R11

      (87) 0x20f183 ADD	$0x18,%R10

      (87) 0x20f187 CMP	%R13,%R11

      (87) 0x20f18a JGE	20f160

      (87) 0x20f18c VMOVUPD	(%R9),%XMM7

      (87) 0x20f191 VSUBPD	-0x10(%R10),%XMM7,%XMM7

      (87) 0x20f197 VMOVAPD	%XMM7,%XMM8

      (87) 0x20f19b VFMADD213SD	%XMM0,%XMM7,%XMM8

      (87) 0x20f1a0 VPERMILPD	$0x1,%XMM7,%XMM9

      (87) 0x20f1a6 VFMADD213SD	%XMM8,%XMM9,%XMM9

      (87) 0x20f1ab VMOVSD	0x10(%R9),%XMM8

      (87) 0x20f1b1 VSUBSD	(%R10),%XMM8,%XMM8

      (87) 0x20f1b6 VFMADD231SD	%XMM8,%XMM8,%XMM9

      (87) 0x20f1bb VUCOMISD	%XMM0,%XMM9

      (87) 0x20f1bf JBE	20f180

      (87) 0x20f1c1 VMOVSD	(%R15),%XMM10

      (87) 0x20f1c6 VUCOMISD	%XMM9,%XMM10

      (87) 0x20f1cb JB	20f180

      (87) 0x20f1cd VDIVSD	%XMM9,%XMM1,%XMM9

      (87) 0x20f1d2 MOV	0x30(%RSI),%RBX

      (87) 0x20f1d6 VMOVSD	(%RBX,%RAX,8),%XMM12

      (87) 0x20f1db VMULSD	%XMM9,%XMM9,%XMM10

      (87) 0x20f1e0 VMULSD	%XMM10,%XMM9,%XMM10

      (87) 0x20f1e5 VMULSD	(%R14),%XMM10,%XMM10

      (87) 0x20f1ea VADDSD	%XMM2,%XMM10,%XMM11

      (87) 0x20f1ee VFMSUB213SD	(%RDX),%XMM10,%XMM11

      (87) 0x20f1f3 VFMADD231SD	%XMM3,%XMM11,%XMM12

      (87) 0x20f1f8 VMOVSD	%XMM12,(%RBX,%RAX,8)

      (87) 0x20f1fd VFMADD213SD	-0x38(%RBP),%XMM3,%XMM11

      (87) 0x20f203 VMOVSD	%XMM11,-0x38(%RBP)

      (87) 0x20f208 VMULSD	(%RCX),%XMM4,%XMM11

      (87) 0x20f20c MOV	0x28(%RSI),%RBX

      (87) 0x20f210 VMULSD	%XMM11,%XMM10,%XMM11

      (87) 0x20f215 VFMADD213SD	%XMM6,%XMM5,%XMM10

      (87) 0x20f21a VMULSD	%XMM11,%XMM9,%XMM9

      (87) 0x20f21f VMULSD	%XMM9,%XMM10,%XMM9

      (87) 0x20f224 VMOVDDUP	%XMM9,%XMM10

      (87) 0x20f229 VFNMADD213PD	(%RBX,%R12,8),%XMM7,%XMM10

      (87) 0x20f22f VMOVUPD	%XMM10,(%RBX,%R12,8)

      (87) 0x20f235 VFNMADD213SD	0x10(%RBX,%R12,8),%XMM9,%XMM8

      (87) 0x20f23c VMOVSD	%XMM8,0x10(%RBX,%R12,8)

      (87) 0x20f243 JMP	20f180

0x20f250 XOR	%EAX,%EAX

0x20f252 NOPW	%CS:(%RAX,%RAX,1)

  (84) 0x20f260 MOV	-0x70(%RBP),%RSI

  (84) 0x20f264 CMPL	$0,(%RSI,%RAX,4)

  (84) 0x20f268 JS	20f2bc

  (84) 0x20f26a INC	%RAX

  (84) 0x20f26d CMP	%RAX,-0x48(%RBP)

  (84) 0x20f271 JNE	20f260

0x20f273 JMP	20f080

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 173 - 216

--------------------------------------------------------------------------------

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:173-175,ljForce.c:178-178,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.89
CQA cycles if no scalar integer	2.89
CQA cycles if FP arith vectorized	2.89
CQA cycles if fully vectorized	0.53
Front-end cycles	2.33
DIV/SQRT cycles	1.33
P0 cycles	1.25
P1 cycles	1.17
P2 cycles	1.08
P3 cycles	1.17
P4 cycles	2.89
P5 cycles	2.89
P6 cycles	2.89
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.33
Nb uops	14.00
Nb loads	6.33
Nb stores	2.67
Nb stack references	5.67
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.31
Bytes prefetched	0.00
Bytes loaded	41.33
Bytes stored	20.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.67
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.52
Vector-efficiency ratio load	7.29
Vector-efficiency ratio store	11.46
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.03

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:173-175,ljForce.c:178-178,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.27
Front-end cycles	1.50
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.00
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	1.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	9.00
Nb loads	4.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.60
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	12.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:173-175,ljForce.c:178-178,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.75
Front-end cycles	3.33
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.71
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P5, P6, P7,
Function	.omp_outlined..5#0x20eed0
Source	ljForce.c:173-175,ljForce.c:178-178,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.58
Front-end cycles	2.17
DIV/SQRT cycles	1.00
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	7.00
Nb stores	2.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:173-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173-175,178,216.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.89 to 0.53 cycles (5.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 41 bytes. The binary loop is storing 20 bytes.

General properties

nb instructions	14.33
nb uops	14
loop length	58.33
used x86 registers	3.67
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.33 cycles
front end	2.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.33	1.25	1.17	1.08	1.17	2.89	2.89	2.89	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.25	1.17	1.08	1.17	2.89	2.89	2.89	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.33
Dispatch	2.89
Data deps.	0.00
Overall L1	2.89

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	7%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.89 cycles. At this rate:

15% of peak load performance is reached (14.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (6.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:173-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.67 to 1.50 cycles (1.11x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	8
nb uops	9
loop length	32
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.25	1.25	1.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.25	1.25	1.25	1.25	1.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.50
Dispatch	1.67
Data deps.	0.00
Overall L1	1.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.20 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f096

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0x60(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
ADDL $0x40,-0x3c(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.50
LEA 0x1(%RSI),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %RSI,-0x80(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JLE 20ef6e <.omp_outlined..5+0x9e>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMPL $0,-0x48(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JLE 20f080 <.omp_outlined..5+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:173-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.33 cycles (1.20x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	21
nb uops	20
loop length	79
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	1.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.75	1.75	1.50	1.50	1.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.33
Dispatch	4.00
Data deps.	0.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

13% of peak load performance is reached (13.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f096

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
CMPL $0,-0x48(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JLE 20f080 <.omp_outlined..5+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x80(%RSI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RAX,%RDI,4),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV (%RSI,%RDI,8),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 20f250 <.omp_outlined..5+0x380>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVSXD -0x3c(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %EDI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
CLTQ
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JMP 20f100 <.omp_outlined..5+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	.omp_outlined..5#0x20eed0
Source file and lines	ljForce.c:173-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.17 cycles (1.38x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	14
nb uops	13
loop length	64
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	0.75	0.75	0.50	1.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.17
Dispatch	3.00
Data deps.	0.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f096

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
CMPL $0,-0x48(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JLE 20f080 <.omp_outlined..5+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x80(%RSI),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RAX,%RDI,4),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RSI,%RDI,8),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 20f250 <.omp_outlined..5+0x380>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code