OV - exec - Loop 71

	Loop Id: 71	Module: exec	Source: haloExchange.c:633-642	Coverage: 0.04%

0x20bfb0 VMOVD	(%RBX),%XMM11    [2]

0x20bfb4 VMOVD	0xe0(%RBX),%XMM12    [2]

0x20bfbc VPINSRD	$0x1,0x38(%RBX),%XMM11,%XMM11    [2]

0x20bfc3 VPINSRD	$0x1,0x118(%RBX),%XMM12,%XMM12    [2]

0x20bfcd VPINSRD	$0x2,0x70(%RBX),%XMM11,%XMM11    [2]

0x20bfd4 VPINSRD	$0x2,0x150(%RBX),%XMM12,%XMM12    [2]

0x20bfde VPINSRD	$0x3,0xa8(%RBX),%XMM11,%XMM11    [2]

0x20bfe8 VPINSRD	$0x3,0x188(%RBX),%XMM12,%XMM12    [2]

0x20bff2 VMOVDQU	%XMM12,0x10(%RAX,%R13,4)    [1]

0x20bff9 VMOVDQU	%XMM11,(%RAX,%R13,4)    [1]

0x20bfff VMOVD	0x4(%RBX),%XMM11    [2]

0x20c004 VMOVD	0xe4(%RBX),%XMM12    [2]

0x20c00c VPINSRD	$0x1,0x3c(%RBX),%XMM11,%XMM11    [2]

0x20c013 VPINSRD	$0x1,0x11c(%RBX),%XMM12,%XMM12    [2]

0x20c01d VPINSRD	$0x2,0x74(%RBX),%XMM11,%XMM11    [2]

0x20c024 VPINSRD	$0x2,0x154(%RBX),%XMM12,%XMM12    [2]

0x20c02e VPINSRD	$0x3,0xac(%RBX),%XMM11,%XMM11    [2]

0x20c038 VPINSRD	$0x3,0x18c(%RBX),%XMM12,%XMM12    [2]

0x20c042 VMOVDQU	%XMM12,0x10(%RCX,%R13,4)    [4]

0x20c049 VMOVDQU	%XMM11,(%RCX,%R13,4)    [4]

0x20c04f ADD	$0x8,%R13

0x20c053 VMOVUPD	0x8(%RBX),%ZMM11    [2]

0x20c05d VMOVUPD	0x88(%RBX),%ZMM13    [2]

0x20c067 VMOVUPD	0x148(%RBX),%ZMM17    [2]

0x20c071 VMOVUPD	0x48(%RBX),%ZMM12    [2]

0x20c07b VMOVUPD	0xc8(%RBX),%ZMM14    [2]

0x20c085 VMOVUPD	0x108(%RBX),%ZMM16    [2]

0x20c08f VMOVUPD	0x188(%RBX),%ZMM15    [2]

0x20c099 ADD	$0x1c0,%RBX

0x20c0a0 VMOVAPD	%ZMM17,%ZMM18

0x20c0a6 VMOVAPD	%ZMM11,%ZMM20

0x20c0ac VPERMT2PD	%ZMM16,%ZMM0,%ZMM18

0x20c0b2 VMOVAPD	%ZMM13,%ZMM19

0x20c0b8 VPERMT2PD	%ZMM14,%ZMM2,%ZMM19

0x20c0be VPERMT2PD	%ZMM16,%ZMM5,%ZMM17

0x20c0c4 VPERMT2PD	%ZMM12,%ZMM7,%ZMM11

0x20c0ca VPERMT2PD	%ZMM13,%ZMM9,%ZMM14

0x20c0d0 VPERMT2PD	%ZMM12,%ZMM4,%ZMM20

0x20c0d6 VPERMT2PD	%ZMM15,%ZMM1,%ZMM18

0x20c0dc VPERMT2PD	%ZMM16,%ZMM3,%ZMM19

0x20c0e2 VPERMT2PD	%ZMM15,%ZMM6,%ZMM17

0x20c0e8 VPERMT2PD	%ZMM13,%ZMM8,%ZMM11

0x20c0ee VPERMT2PD	%ZMM16,%ZMM10,%ZMM14

0x20c0f4 VMOVUPD	%ZMM20,(%RDX,%R10,1)    [5]

0x20c0fb VMOVUPD	%ZMM18,0x80(%RDX,%R10,1)    [5]

0x20c103 VMOVUPD	%ZMM19,0x40(%RDX,%R10,1)    [5]

0x20c10b VMOVUPD	%ZMM17,0x80(%RSI,%R10,1)    [3]

0x20c113 VMOVUPD	%ZMM14,0x40(%RSI,%R10,1)    [3]

0x20c11b VMOVUPD	%ZMM11,(%RSI,%R10,1)    [3]

0x20c122 ADD	$0xc0,%R10

0x20c129 CMP	%R13,%R11

0x20c12c JNE	20bfb0

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642

--------------------------------------------------------------------------------

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.49
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P9, P10,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	11.38
Front-end cycles	9.50
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	13.33
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	0.00
P8 cycles	17.00
P9 cycles	17.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	57.00
Nb loads	23.00
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.47
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	448.00
Stride 0	0.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	65.96
Vectorization ratio load	30.43
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.85
Vector-efficiency ratio all	61.70
Vector-efficiency ratio load	34.78
Vector-efficiency ratio store	70.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	56.73

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.49
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P9, P10,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	17.00
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	11.38
Front-end cycles	9.50
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	13.33
P5 cycles	13.33
P6 cycles	13.33
P7 cycles	0.00
P8 cycles	17.00
P9 cycles	17.00
P10 cycles	0.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	52.00
Nb uops	57.00
Nb loads	23.00
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.47
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	448.00
Stride 0	0.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	65.96
Vectorization ratio load	30.43
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.85
Vector-efficiency ratio all	61.70
Vector-efficiency ratio load	34.78
Vector-efficiency ratio store	70.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	56.73

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 61% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 11.37 cycles (1.49x speedup).

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 6 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	52
nb uops	57
loop length	386
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	11.00	11.00	11.00	0.00	17.00	17.00	0.00	8.00	8.00
cycles	1.00	1.00	0.75	0.75	0.50	13.33	13.33	13.33	0.00	17.00	17.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.50
Dispatch	17.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	20%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	65%
load	30%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	10%
load	6%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	61%
load	34%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

31% of peak load performance is reached (30.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
41% of peak store performance is reached (26.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20bfb0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVD (%RBX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VMOVD 0xe0(%RBX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VPINSRD $0x1,0x38(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x1,0x118(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x70(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x150(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0xa8(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0x188(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VMOVDQU %XMM12,0x10(%RAX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVDQU %XMM11,(%RAX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVD 0x4(%RBX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VMOVD 0xe4(%RBX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VPINSRD $0x1,0x3c(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x1,0x11c(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x74(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x154(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0xac(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0x18c(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VMOVDQU %XMM12,0x10(%RCX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVDQU %XMM11,(%RCX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
ADD $0x8,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x8(%RBX),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x88(%RBX),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x148(%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x48(%RBX),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc8(%RBX),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x108(%RBX),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x188(%RBX),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
ADD $0x1c0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM11,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM16,%ZMM0,%ZMM18	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM13,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM14,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM5,%ZMM17	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM12,%ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM13,%ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM20	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM15,%ZMM1,%ZMM18	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM3,%ZMM19	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM15,%ZMM6,%ZMM17	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM13,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM10,%ZMM14	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM20,(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM18,0x80(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM19,0x40(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM17,0x80(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM14,0x40(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM11,(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0xc0,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 20bfb0 <sortAtomsInCell+0x300>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

gain
potential
hint
expert

Vectorization

Details

65% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

30% of SSE/AVX loads are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 6 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	52
nb uops	57
loop length	386
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	11.00	11.00	11.00	0.00	17.00	17.00	0.00	8.00	8.00
cycles	1.00	1.00	0.75	0.75	0.50	13.33	13.33	13.33	0.00	17.00	17.00	0.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.50
Dispatch	17.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	20%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	65%
load	30%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	10%
load	6%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	61%
load	34%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	56%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

31% of peak load performance is reached (30.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
41% of peak store performance is reached (26.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20bfb0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVD (%RBX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VMOVD 0xe0(%RBX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VPINSRD $0x1,0x38(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x1,0x118(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x70(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x150(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0xa8(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0x188(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VMOVDQU %XMM12,0x10(%RAX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVDQU %XMM11,(%RAX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVD 0x4(%RBX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VMOVD 0xe4(%RBX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	8	0.50
VPINSRD $0x1,0x3c(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x1,0x11c(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x74(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x2,0x154(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0xac(%RBX),%XMM11,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VPINSRD $0x3,0x18c(%RBX),%XMM12,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	1	0.50
VMOVDQU %XMM12,0x10(%RCX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
VMOVDQU %XMM11,(%RCX,%R13,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
ADD $0x8,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x8(%RBX),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x88(%RBX),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x148(%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x48(%RBX),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0xc8(%RBX),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x108(%RBX),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
VMOVUPD 0x188(%RBX),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	1
ADD $0x1c0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM11,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM16,%ZMM0,%ZMM18	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM13,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM14,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM5,%ZMM17	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM12,%ZMM7,%ZMM11	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM13,%ZMM9,%ZMM14	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM12,%ZMM4,%ZMM20	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM15,%ZMM1,%ZMM18	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM3,%ZMM19	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM15,%ZMM6,%ZMM17	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM13,%ZMM8,%ZMM11	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM16,%ZMM10,%ZMM14	1	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM20,(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM18,0x80(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM19,0x40(%RDX,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM17,0x80(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM14,0x40(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
VMOVUPD %ZMM11,(%RSI,%R10,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	1	1	5	2
ADD $0xc0,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %R13,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 20bfb0 <sortAtomsInCell+0x300>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code