OV - exec - Loop 30

	Loop Id: 30	Module: exec	Source: timestep.c:74-78	Coverage: 0.01%

0x211d30 VMOVUPD	(%R12,%RCX,1),%ZMM18    [3]

0x211d37 VMOVUPD	0x40(%R12,%RCX,1),%YMM19    [3]

0x211d3f VMOVUPD	0x40(%R15,%RCX,1),%YMM22    [1]

0x211d47 VBROADCASTSD	(%RBX),%YMM17    [2]

0x211d4d VMOVAPD	%ZMM18,%ZMM20

0x211d53 VMOVAPD	%ZMM18,%ZMM21

0x211d59 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

0x211d5f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

0x211d65 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

0x211d6b VMOVUPD	(%R15,%RCX,1),%ZMM19    [1]

0x211d72 VMOVAPD	%ZMM19,%ZMM23

0x211d78 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

0x211d7e VMOVAPD	%ZMM19,%ZMM24

0x211d84 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

0x211d8a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

0x211d90 VFMADD231PD	%YMM20,%YMM17,%YMM23

0x211d96 VFMADD231PD	%YMM21,%YMM17,%YMM24

0x211d9c VFMADD231PD	%YMM18,%YMM17,%YMM19

0x211da2 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

0x211da9 VMOVAPD	%ZMM17,%ZMM18

0x211daf VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

0x211db5 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

0x211dbb VMOVUPD	%ZMM17,(%R15,%RCX,1)    [1]

0x211dc2 VMOVUPD	%YMM18,0x40(%R15,%RCX,1)    [1]

0x211dca ADD	$0x60,%RCX

0x211dce ADD	$0x4,%R8

0x211dd2 JNE	211d30

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.89
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.89
Bottlenecks	P9, P10,
Function	.omp_outlined.#0x211980
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	8.25
Front-end cycles	4.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	0.00
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	5.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.82
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.82
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	80.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.33
Vector-efficiency ratio all	81.77
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	90.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.89
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.89
Bottlenecks	P9, P10,
Function	.omp_outlined.#0x211980
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	8.25
Front-end cycles	4.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	0.00
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	5.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.82
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.82
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	80.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.33
Vector-efficiency ratio all	81.77
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	90.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x211980
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

It is intermediate loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 4.50 cycles (1.89x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 12 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 3 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 3 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	27
loop length	168
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	13
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.33	2.33	2.33	3.00	8.50	8.50	0.00	1.50	1.50
cycles	0.50	0.50	0.25	0.25	0.50	3.00	3.00	3.00	3.00	8.50	8.50	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Dispatch	8.50
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	95%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

all	81%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

24% of peak load performance is reached (23.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 211d30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RCX,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RCX,1),%YMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.50
VMOVUPD 0x40(%R15,%RCX,1),%YMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.50
VBROADCASTSD (%RBX),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	4	0.50
VMOVAPD %ZMM18,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM0,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD (%R15,%RCX,1),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVAPD %ZMM19,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM0,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM19,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM22,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VFMADD231PD %YMM20,%YMM17,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VFMADD231PD %YMM21,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VFMADD231PD %YMM18,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM3,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM4,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM17,(%R15,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %YMM18,0x40(%R15,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
ADD $0x60,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 211d30 <.omp_outlined.+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined.#0x211980
Source file and lines	timestep.c:74-78
Module	exec

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 12 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 3 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 3 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	27
loop length	168
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	13
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	2.33	2.33	2.33	3.00	8.50	8.50	0.00	1.50	1.50
cycles	0.50	0.50	0.25	0.25	0.50	3.00	3.00	3.00	3.00	8.50	8.50	0.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Dispatch	8.50
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	95%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

all	81%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

24% of peak load performance is reached (23.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (11.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 211d30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%RCX,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%RCX,1),%YMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.50
VMOVUPD 0x40(%R15,%RCX,1),%YMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	0.50
VBROADCASTSD (%RBX),%YMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	4	0.50
VMOVAPD %ZMM18,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM0,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD (%R15,%RCX,1),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVAPD %ZMM19,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM0,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM19,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM22,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VFMADD231PD %YMM20,%YMM17,%YMM23	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VFMADD231PD %YMM21,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VFMADD231PD %YMM18,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	1
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM3,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM19,%ZMM4,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM17,(%R15,%RCX,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %YMM18,0x40(%R15,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
ADD $0x60,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x4,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 211d30 <.omp_outlined.+0x3b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Unrolling/vectorization cost

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Vectorization

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Execution units bottlenecks

Workaround

FMA

Complex instructions

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Slow data structures access

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Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code