OV - exec - Function putAtomInBox

	Function: putAtomInBox	Module: exec	Source: linkCells.c:173-378 [...]	Coverage: 0.09%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 173 - 378

--------------------------------------------------------------------------------

173: {

174:    real_t xyz[3] = {x,y,z};

175:

176:    // Find correct box.

177:    int iBox = getBoxFromCoord(boxes, xyz);

178:    int iOff = iBox*MAXATOMS;

179:    iOff += boxes->nAtoms[iBox];

180:

181:    // assign values to array elements

182:    if (iBox < boxes->nLocalBoxes)

183:       atoms->nLocal++;

184:    boxes->nAtoms[iBox]++;

185:    atoms->gid[iOff] = gid;

186:    atoms->iSpecies[iOff] = iType;

187:

188:    atoms->r[iOff][0] = x;

189:    atoms->r[iOff][1] = y;

190:    atoms->r[iOff][2] = z;

191:

192:    atoms->p[iOff][0] = px;

193:    atoms->p[iOff][1] = py;

194:    atoms->p[iOff][2] = pz;

195: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

0x20e1c0 PUSH	%RBP

0x20e1c1 MOV	%RSP,%RBP

0x20e1c4 PUSH	%R15

0x20e1c6 PUSH	%R14

0x20e1c8 PUSH	%R12

0x20e1ca PUSH	%RBX

0x20e1cb SUB	$0x40,%RSP

0x20e1cf VMOVSD	%XMM3,-0x30(%RBP)

0x20e1d4 VUNPCKLPD	%XMM2,%XMM1,%XMM3

0x20e1d8 VSUBPD	0x20(%RDI),%XMM3,%XMM3

0x20e1dd VMOVSD	%XMM5,-0x40(%RBP)

0x20e1e2 VMOVSD	0x30(%RDI),%XMM5

0x20e1e7 VMOVSD	%XMM4,-0x38(%RBP)

0x20e1ec MOV	%ECX,%R14D

0x20e1ef MOV	%EDX,%R15D

0x20e1f2 MOV	%RSI,%RBX

0x20e1f5 MOV	%RDI,%R12

0x20e1f8 VMOVSD	%XMM0,-0x28(%RBP)

0x20e1fd VMULPD	0x68(%RDI),%XMM3,%XMM3

0x20e202 VUCOMISD	%XMM0,%XMM5

0x20e206 VROUNDPD	$0x9,%XMM3,%XMM3

0x20e20c VCVTTPD2DQ	%XMM3,%XMM4

0x20e210 JBE	20e238

0x20e212 VSUBSD	0x18(%R12),%XMM0,%XMM3

0x20e219 MOV	(%R12),%ECX

0x20e21d VMULSD	0x60(%R12),%XMM3,%XMM3

0x20e224 LEA	-0x1(%RCX),%ESI

0x20e227 VROUNDSD	$0x9,%XMM3,%XMM3,%XMM3

0x20e22d VCVTTSD2SI	%XMM3,%EAX

0x20e231 CMP	%EAX,%ECX

0x20e233 CMOVNE	%EAX,%ESI

0x20e236 JMP	20e23c

0x20e238 MOV	(%R12),%ESI

0x20e23c MOV	0x4(%R12),%RAX

0x20e241 VMOVSD	0x38(%R12),%XMM0

0x20e248 VMOVD	%XMM4,%EDX

0x20e24c VMOVAPD	%XMM1,-0x50(%RBP)

0x20e251 VMOVAPD	%XMM2,-0x60(%RBP)

0x20e256 VMOVQ	%RAX,%XMM3

0x20e25b LEA	-0x1(%RAX),%EDI

0x20e25e VPCMPEQD	%XMM4,%XMM3,%K0

0x20e264 KMOVD	%K0,%ECX

0x20e268 KSHIFTRB	$0x1,%K0,%K1

0x20e26e TEST	$0x1,%CL

0x20e271 VPEXTRD	$0x1,%XMM4,%ECX

0x20e277 CMOVNE	%EDI,%EDX

0x20e27a VUCOMISD	%XMM1,%XMM0

0x20e27e VMOVSD	0x40(%R12),%XMM0

0x20e285 KMOVD	%K1,%EDI

0x20e289 CMOVBE	%EAX,%EDX

0x20e28c SHR	$0x20,%RAX

0x20e290 TEST	$0x1,%DIL

0x20e294 MOV	%R12,%RDI

0x20e297 LEA	-0x1(%RAX),%R8D

0x20e29b CMOVNE	%R8D,%ECX

0x20e29f VUCOMISD	%XMM2,%XMM0

0x20e2a3 CMOVBE	%EAX,%ECX

0x20e2a6 CALL	20e0b0 <getBoxFromTuple>

0x20e2ab MOV	0x78(%R12),%RCX

0x20e2b0 MOV	%EAX,%EDX

0x20e2b2 MOV	(%RCX,%RDX,4),%ESI

0x20e2b5 MOV	%ESI,%EDI

0x20e2b7 CMP	%EAX,0xc(%R12)

0x20e2bc JLE	20e2c3

0x20e2be INCL	(%RBX)

0x20e2c0 MOV	(%RCX,%RDX,4),%EDI

0x20e2c3 INC	%EDI

0x20e2c5 MOV	%EDX,%EAX

0x20e2c7 SAL	$0x6,%EAX

0x20e2ca VMOVSD	-0x28(%RBP),%XMM0

0x20e2cf VMOVSD	-0x30(%RBP),%XMM1

0x20e2d4 VMOVSD	-0x38(%RBP),%XMM2

0x20e2d9 MOV	%EDI,(%RCX,%RDX,4)

0x20e2dc ADD	%EAX,%ESI

0x20e2de MOV	0x8(%RBX),%RAX

0x20e2e2 MOVSXD	%ESI,%RCX

0x20e2e5 MOV	%R15D,(%RAX,%RCX,4)

0x20e2e9 MOV	0x10(%RBX),%RAX

0x20e2ed MOV	%R14D,(%RAX,%RCX,4)

0x20e2f1 SAL	$0x3,%RCX

0x20e2f5 MOV	0x18(%RBX),%RAX

0x20e2f9 LEA	(%RCX,%RCX,2),%RCX

0x20e2fd VMOVSD	%XMM0,(%RAX,%RCX,1)

0x20e302 VMOVAPS	-0x50(%RBP),%XMM0

0x20e307 VMOVSD	%XMM0,0x8(%RAX,%RCX,1)

0x20e30d VMOVAPS	-0x60(%RBP),%XMM0

0x20e312 VMOVSD	%XMM0,0x10(%RAX,%RCX,1)

0x20e318 MOV	0x20(%RBX),%RAX

0x20e31c VMOVSD	%XMM1,(%RAX,%RCX,1)

0x20e321 VMOVSD	-0x40(%RBP),%XMM1

0x20e326 VMOVSD	%XMM2,0x8(%RAX,%RCX,1)

0x20e32c VMOVSD	%XMM1,0x10(%RAX,%RCX,1)

0x20e332 ADD	$0x40,%RSP

0x20e336 POP	%RBX

0x20e337 POP	%R12

0x20e339 POP	%R14

0x20e33b POP	%R15

0x20e33d POP	%RBP

0x20e33e RET

0x20e33f NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:173-378
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:173-195,352-365,371,378.

This function has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.50 to 2.66 cycles (6.21x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
41% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
VCVTTSD2SI: 1 occurrences
VPEXTRD: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

2.50: addition or subtraction
2.50: multiply

The binary function is loading 192 bytes (24 double precision FP elements). The binary function is storing 126 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	99
loop length	359.50
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.63	5.63	5.50	5.50	3.25	12.67	12.67	12.67	1.25	3.25	4.25	4.25	9.75	9.75
cycles	5.63	5.63	5.50	5.50	3.25	12.67	12.67	12.67	1.25	3.25	4.25	4.25	9.75	9.75

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	12.67
Overall L1	16.50

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	33%
store	16%
mul	75%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	29%

INT+FP

all	20%
load	26%
store	12%
mul	75%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	16%
store	14%
mul	21%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	14%
store	12%
mul	21%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

12% of peak load performance is reached (11.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.65 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.50 to 9.00 cycles (1.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.50 to 2.77 cycles (6.32x speedup).

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
VCVTTSD2SI: 1 occurrences
VPEXTRD: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 204 bytes (25 double precision FP elements). The binary function is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	105
loop length	379
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.00	6.00	3.50	13.33	13.33	13.33	1.50	3.50	5.00	5.00	10.00	10.00
cycles	6.25	6.25	6.00	6.00	3.50	13.33	13.33	13.33	1.50	3.50	5.00	5.00	10.00	10.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.50
Dispatch	13.33
Overall L1	17.50

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	24%
load	30%
store	16%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	18%
load	25%
store	12%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	16%
store	14%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	14%
store	12%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.50 cycles. At this rate:

12% of peak load performance is reached (11.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.31 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.50 to 13.33 cycles (1.31x speedup).

ASM code

In the binary file, the address of the function is: 20e1c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VUNPCKLPD %XMM2,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD 0x20(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMULPD 0x68(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VUCOMISD %XMM0,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VROUNDPD $0x9,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTPD2DQ %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JBE 20e238 <putAtomInBox+0x78>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD 0x18(%R12),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOV (%R12),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD 0x60(%R12),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
LEA -0x1(%RCX),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VROUNDSD $0x9,%XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM3,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %EAX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %EAX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
JMP 20e23c <putAtomInBox+0x7c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x38(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVD %XMM4,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
VMOVAPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVQ %RAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%RAX),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPCMPEQD %XMM4,%XMM3,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
KMOVD %K0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
KSHIFTRB $0x1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
TEST $0x1,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPEXTRD $0x1,%XMM4,%ECX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
CMOVNE %EDI,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x40(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
KMOVD %K1,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
CMOVBE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
CMOVBE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 20e0b0 <getBoxFromTuple>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EAX,0xc(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 20e2c3 <putAtomInBox+0x103>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INCL (%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%RCX,%RDX,4),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x60(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM1,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM2,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 9.00 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTSD2SI: 1 occurrences
VPEXTRD: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 196 bytes (24 double precision FP elements). The binary function is storing 124 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	102
loop length	374
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	5.75	5.75	3.50	12.67	12.67	12.67	1.50	3.50	5.00	5.00	10.00	10.00
cycles	6.00	6.00	5.75	5.75	3.50	12.67	12.67	12.67	1.50	3.50	5.00	5.00	10.00	10.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Dispatch	12.67
Overall L1	17.00

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	24%
load	30%
store	16%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	19%
load	26%
store	13%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	16%
store	14%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	15%
store	12%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

12% of peak load performance is reached (11.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20e1c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VUNPCKLPD %XMM2,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD 0x20(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMULPD 0x68(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VUCOMISD %XMM0,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VROUNDPD $0x9,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTPD2DQ %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JBE 20e238 <putAtomInBox+0x78>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD 0x18(%R12),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOV (%R12),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMULSD 0x60(%R12),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
LEA -0x1(%RCX),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VROUNDSD $0x9,%XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM3,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %EAX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %EAX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
JMP 20e23c <putAtomInBox+0x7c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x38(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVD %XMM4,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
VMOVAPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVQ %RAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%RAX),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPCMPEQD %XMM4,%XMM3,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
KMOVD %K0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
KSHIFTRB $0x1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
TEST $0x1,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPEXTRD $0x1,%XMM4,%ECX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
CMOVNE %EDI,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x40(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
KMOVD %K1,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
CMOVBE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
CMOVBE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 20e0b0 <getBoxFromTuple>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EAX,0xc(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 20e2c3 <putAtomInBox+0x103>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x60(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM1,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM2,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 8.50 cycles (1.88x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
VPEXTRD: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 188 bytes (23 double precision FP elements). The binary function is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	90
nb uops	96
loop length	345
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.00 cycles
front end	16.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.25	5.25	5.25	5.25	3.00	12.67	12.67	12.67	1.00	3.00	3.50	3.50	9.50	9.50
cycles	5.25	5.25	5.25	5.25	3.00	12.67	12.67	12.67	1.00	3.00	3.50	3.50	9.50	9.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.00
Dispatch	12.67
Overall L1	16.00

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	27%
load	36%
store	16%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	20%
load	26%
store	12%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	17%
store	14%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	14%
store	12%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

12% of peak load performance is reached (11.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20e1c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VUNPCKLPD %XMM2,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD 0x20(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMULPD 0x68(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VUCOMISD %XMM0,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VROUNDPD $0x9,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTPD2DQ %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JBE 20e238 <putAtomInBox+0x78>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x38(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVD %XMM4,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
VMOVAPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVQ %RAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%RAX),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPCMPEQD %XMM4,%XMM3,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
KMOVD %K0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
KSHIFTRB $0x1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
TEST $0x1,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPEXTRD $0x1,%XMM4,%ECX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
CMOVNE %EDI,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x40(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
KMOVD %K1,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
CMOVBE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
CMOVBE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 20e0b0 <getBoxFromTuple>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EAX,0xc(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 20e2c3 <putAtomInBox+0x103>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INCL (%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%RCX,%RDX,4),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x60(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM1,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM2,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.50 to 8.50 cycles (1.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
23% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPEXTRD: 1 occurrences
VUCOMISD: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 180 bytes (22 double precision FP elements). The binary function is storing 124 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	88
nb uops	93
loop length	340
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.50 cycles
front end	15.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.00	5.00	5.00	5.00	3.00	12.00	12.00	12.00	1.00	3.00	3.50	3.50	9.50	9.50
cycles	5.00	5.00	5.00	5.00	3.00	12.00	12.00	12.00	1.00	3.00	3.50	3.50	9.50	9.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Dispatch	12.00
Overall L1	15.50

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	27%
load	36%
store	16%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	21%
load	28%
store	13%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	17%
store	14%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	14%
store	12%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.50 cycles. At this rate:

12% of peak load performance is reached (11.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20e1c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VUNPCKLPD %XMM2,%XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VSUBPD 0x20(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD 0x30(%RDI),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMULPD 0x68(%RDI),%XMM3,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VUCOMISD %XMM0,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VROUNDPD $0x9,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTPD2DQ %XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JBE 20e238 <putAtomInBox+0x78>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD 0x38(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVD %XMM4,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
VMOVAPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVQ %RAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	1
LEA -0x1(%RAX),%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPCMPEQD %XMM4,%XMM3,%K0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
KMOVD %K0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
KSHIFTRB $0x1,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
TEST $0x1,%CL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPEXTRD $0x1,%XMM4,%ECX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
CMOVNE %EDI,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM1,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x40(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
KMOVD %K1,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	1
CMOVBE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
VUCOMISD %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	1
CMOVBE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 20e0b0 <getBoxFromTuple>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %EAX,0xc(%R12)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 20e2c3 <putAtomInBox+0x103>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVAPS -0x60(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM1,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM2,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD %XMM1,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x40,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
○putAtomInBox	0.09	0.01

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Cycles summary

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Cycles and memory resources usage

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Vectorization