OV - exec - Function .omp_outlined..6#0x212240

	Function: .omp_outlined..6#0x212240	Module: exec	Source: timestep.c:152-154	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 152 - 154

--------------------------------------------------------------------------------

152:    #pragma omp parallel for

153:    for (int ii=0; ii<sim->boxes->nTotalBoxes; ++ii)

154:       sortAtomsInCell(sim->atoms, sim->boxes, ii);

0x212240 PUSH	%RBP

0x212241 MOV	%RSP,%RBP

0x212244 PUSH	%R15

0x212246 PUSH	%R14

0x212248 PUSH	%R12

0x21224a PUSH	%RBX

0x21224b SUB	$0x10,%RSP

0x21224f MOV	(%RDX),%RAX

0x212252 MOV	0x18(%RAX),%RAX

0x212256 MOV	0x14(%RAX),%R12D

0x21225a TEST	%R12D,%R12D

0x21225d JLE	2122ff

0x212263 MOV	(%RDI),%R14D

0x212266 DEC	%R12D

0x212269 MOV	%RDX,%RBX

0x21226c MOVL	$0,-0x28(%RBP)

0x212273 MOVL	$0x1,-0x30(%RBP)

0x21227a MOVL	$0,-0x2c(%RBP)

0x212281 MOV	%R12D,-0x24(%RBP)

0x212285 SUB	$0x8,%RSP

0x212289 LEA	-0x30(%RBP),%RAX

0x21228d LEA	0x1b34(%RIP),%RDI

0x212294 LEA	-0x2c(%RBP),%RCX

0x212298 LEA	-0x28(%RBP),%R8

0x21229c LEA	-0x24(%RBP),%R9

0x2122a0 MOV	%R14D,%ESI

0x2122a3 MOV	$0x22,%EDX

0x2122a8 PUSH	$0x1

0x2122aa PUSH	$0x1

0x2122ac PUSH	%RAX

0x2122ad CALL	2127e0 <@plt_start@+0x180>

0x2122b2 ADD	$0x20,%RSP

0x2122b6 MOV	-0x24(%RBP),%EAX

0x2122b9 MOV	-0x28(%RBP),%R15D

0x2122bd CMP	%R12D,%EAX

0x2122c0 CMOVL	%EAX,%R12D

0x2122c4 MOV	%R12D,-0x24(%RBP)

0x2122c8 CMP	%R12D,%R15D

0x2122cb JG	2122f0

0x2122cd NOPL	(%RAX)

(35) 0x2122d0 MOV	(%RBX),%RAX

(35) 0x2122d3 MOV	%R15D,%EDX

(35) 0x2122d6 MOV	0x18(%RAX),%RSI

(35) 0x2122da MOV	0x20(%RAX),%RDI

(35) 0x2122de CALL	20bcb0 <sortAtomsInCell>

(35) 0x2122e3 LEA	0x1(%R15),%EAX

(35) 0x2122e7 CMP	-0x24(%RBP),%R15D

(35) 0x2122eb MOV	%EAX,%R15D

(35) 0x2122ee JL	2122d0

0x2122f0 LEA	0x1ae9(%RIP),%RDI

0x2122f7 MOV	%R14D,%ESI

0x2122fa CALL	2127f0 <@plt_start@+0x190>

0x2122ff ADD	$0x10,%RSP

0x212303 POP	%RBX

0x212304 POP	%R12

0x212306 POP	%R14

0x212308 POP	%R15

0x21230a POP	%RBP

0x21230b RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	timestep.c:152-154
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:152-154.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.53 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	50
nb uops	51
loop length	172
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.75	4.75	4.50	4.50	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.75	4.75	4.50	4.50	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.75
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (3.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 4.75 cycles (1.79x speedup).

ASM code

In the binary file, the address of the function is: 212240

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x14(%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 2122ff <.omp_outlined..6+0xbf>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1b34(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x24(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 2127e0 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x24(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x28(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R12D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JG 2122f0 <.omp_outlined..6+0xb0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
LEA 0x1ae9(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 2127f0 <@plt_start@+0x190>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50

Source file and lines	timestep.c:152-154
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:152-154.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	50
nb uops	51
loop length	172
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.75	4.75	4.50	4.50	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.75	4.75	4.50	4.50	2.50	4.33	4.33	4.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.75
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (3.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.35 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 212240

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x14(%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 2122ff <.omp_outlined..6+0xbf>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x1b34(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x24(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 2127e0 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x24(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV -0x28(%RBP),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R12D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JG 2122f0 <.omp_outlined..6+0xb0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
LEA 0x1ae9(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 2127f0 <@plt_start@+0x190>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..6#0x212240–	0.01	0
○Loop 35 - timestep.c:153-154 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code