OV - exec - Function .omp_outlined.#0x211980

	Function: .omp_outlined.#0x211980	Module: exec	Source: timestep.c:71-78	Coverage: 1.32%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x211980 PUSH	%RBP

0x211981 MOV	%RSP,%RBP

0x211984 PUSH	%R15

0x211986 PUSH	%R14

0x211988 PUSH	%R13

0x21198a PUSH	%R12

0x21198c PUSH	%RBX

0x21198d SUB	$0x48,%RSP

0x211991 MOV	(%RDX),%R14D

0x211994 TEST	%R14D,%R14D

0x211997 JLE	211a1f

0x21199d MOV	(%RDI),%ESI

0x21199f DEC	%R14D

0x2119a2 MOV	%R8,%RBX

0x2119a5 MOV	%RCX,%R15

0x2119a8 MOVL	$0,-0x34(%RBP)

0x2119af MOVL	$0x1,-0x4c(%RBP)

0x2119b6 MOVL	$0,-0x48(%RBP)

0x2119bd MOV	%R14D,-0x30(%RBP)

0x2119c1 SUB	$0x8,%RSP

0x2119c5 LEA	-0x4c(%RBP),%RAX

0x2119c9 LEA	0x2308(%RIP),%RDI

0x2119d0 LEA	-0x48(%RBP),%RCX

0x2119d4 LEA	-0x34(%RBP),%R8

0x2119d8 LEA	-0x30(%RBP),%R9

0x2119dc MOV	%ESI,-0x44(%RBP)

0x2119df MOV	$0x22,%EDX

0x2119e4 PUSH	$0x1

0x2119e6 PUSH	$0x1

0x2119e8 PUSH	%RAX

0x2119e9 CALL	2127e0 <@plt_start@+0x180>

0x2119ee ADD	$0x20,%RSP

0x2119f2 MOV	-0x30(%RBP),%EAX

0x2119f5 CMP	%R14D,%EAX

0x2119f8 CMOVL	%EAX,%R14D

0x2119fc MOVSXD	-0x34(%RBP),%RAX

0x211a00 MOV	%R14D,-0x30(%RBP)

0x211a04 MOV	%RAX,-0x60(%RBP)

0x211a08 CMP	%R14D,%EAX

0x211a0b JLE	211a2e

0x211a0d MOV	-0x44(%RBP),%ESI

0x211a10 LEA	0x22d9(%RIP),%RDI

0x211a17 VZEROUPPER

0x211a1a CALL	2127f0 <@plt_start@+0x190>

0x211a1f ADD	$0x48,%RSP

0x211a23 POP	%RBX

0x211a24 POP	%R12

0x211a26 POP	%R13

0x211a28 POP	%R14

0x211a2a POP	%R15

0x211a2c POP	%RBP

0x211a2d RET

0x211a2e MOV	(%R15),%RDI

0x211a31 VMOVAPD	-0xcf79(%RIP),%YMM0

0x211a39 VMOVAPD	-0xcfc1(%RIP),%YMM1

0x211a41 VMOVAPD	-0xcfa9(%RIP),%YMM2

0x211a49 VMOVAPD	-0xcf51(%RIP),%YMM3

0x211a51 VMOVAPD	-0xc55b(%RIP),%ZMM4

0x211a5b VMOVAPD	-0xc865(%RIP),%ZMM5

0x211a65 VMOVAPD	-0xc82f(%RIP),%ZMM6

0x211a6f VMOVAPD	-0xc7f9(%RIP),%ZMM7

0x211a79 VMOVAPD	-0xc7c3(%RIP),%ZMM8

0x211a83 VMOVAPD	-0xc78d(%RIP),%ZMM9

0x211a8d VMOVAPD	-0xc757(%RIP),%ZMM10

0x211a97 VMOVAPD	-0xc721(%RIP),%ZMM11

0x211aa1 VMOVAPD	-0xc6eb(%RIP),%ZMM12

0x211aab VMOVAPD	-0xc6b5(%RIP),%ZMM13

0x211ab5 VMOVAPD	-0xc67f(%RIP),%ZMM14

0x211abf VMOVAPD	-0xc649(%RIP),%ZMM15

0x211ac9 VMOVAPD	-0xc613(%RIP),%ZMM16

0x211ad3 MOV	-0x60(%RBP),%R10

0x211ad7 MOVSXD	%R14D,%RAX

0x211ada XOR	%R9D,%R9D

0x211add MOV	%RAX,-0x70(%RBP)

0x211ae1 LEA	0x8(%RBX),%RAX

0x211ae5 MOV	%RAX,-0x68(%RBP)

0x211ae9 MOV	0x18(%RDI),%RCX

0x211aed MOV	%R10D,%ESI

0x211af0 SAL	$0x6,%ESI

0x211af3 MOV	%RDI,-0x58(%RBP)

0x211af7 MOV	0x78(%RCX),%R8

0x211afb MOV	%R8,-0x40(%RBP)

0x211aff JMP	211b27

(27) 0x211b10 LEA	0x1(%R10),%RAX

(27) 0x211b14 ADD	$0x40,%ESI

(27) 0x211b17 INC	%R9D

(27) 0x211b1a CMP	-0x70(%RBP),%R10

(27) 0x211b1e MOV	%RAX,%R10

(27) 0x211b21 JGE	211a0d

(27) 0x211b27 MOV	(%R8,%R10,4),%R11D

(27) 0x211b2b TEST	%R11D,%R11D

(27) 0x211b2e JLE	211b10

(27) 0x211b30 MOV	0x20(%RDI),%RCX

(27) 0x211b34 MOVSXD	%ESI,%R13

(27) 0x211b37 XOR	%R14D,%R14D

(27) 0x211b3a MOV	0x20(%RCX),%R15

(27) 0x211b3e MOV	0x28(%RCX),%R12

(27) 0x211b42 LEA	-0x1(%R11),%ECX

(27) 0x211b46 CMP	$0x3,%ECX

(27) 0x211b49 JB	211df0

(27) 0x211b4f MOV	-0x60(%RBP),%RAX

(27) 0x211b53 LEA	(%RAX,%R9,1),%EDX

(27) 0x211b57 SAL	$0x6,%EDX

(27) 0x211b5a MOVSXD	%EDX,%RDX

(27) 0x211b5d LEA	(,%RDX,8),%R8

(27) 0x211b65 ADD	%RCX,%RDX

(27) 0x211b68 SAL	$0x3,%RDX

(27) 0x211b6c LEA	(%R8,%R8,2),%R8

(27) 0x211b70 LEA	(%RDX,%RDX,2),%RDX

(27) 0x211b74 LEA	(%R15,%R8,1),%RDI

(27) 0x211b78 ADD	%R12,%R8

(27) 0x211b7b CMP	-0x68(%RBP),%RDI

(27) 0x211b7f LEA	0x18(%R15,%RDX,1),%RAX

(27) 0x211b84 LEA	0x18(%R12,%RDX,1),%RDX

(27) 0x211b89 SETBB	-0x2a(%RBP)

(27) 0x211b8d CMP	%RBX,%RAX

(27) 0x211b90 SETAB	-0x29(%RBP)

(27) 0x211b94 CMP	%RDX,%RDI

(27) 0x211b97 MOVZX	-0x29(%RBP),%EDI

(27) 0x211b9b SETB	%DL

(27) 0x211b9e CMP	%RAX,%R8

(27) 0x211ba1 SETB	%R8B

(27) 0x211ba5 TEST	%DIL,-0x2a(%RBP)

(27) 0x211ba9 JNE	211bcc

(27) 0x211bab AND	%R8B,%DL

(27) 0x211bae MOV	-0x58(%RBP),%RDI

(27) 0x211bb2 MOV	-0x40(%RBP),%R8

(27) 0x211bb6 JNE	211df0

(27) 0x211bbc LEA	0x1(%RCX),%RDX

(27) 0x211bc0 CMP	$0x7,%ECX

(27) 0x211bc3 JAE	211bd9

(27) 0x211bc5 XOR	%ECX,%ECX

(27) 0x211bc7 JMP	211d0b

(27) 0x211bcc MOV	-0x58(%RBP),%RDI

(27) 0x211bd0 MOV	-0x40(%RBP),%R8

(27) 0x211bd4 JMP	211df0

(27) 0x211bd9 LEA	(,%R13,8),%RAX

(27) 0x211be1 MOV	%RDX,%RCX

(27) 0x211be4 AND	$-0x8,%RCX

(27) 0x211be8 MOV	%RCX,%R8

(27) 0x211beb LEA	(%RAX,%RAX,2),%R14

(27) 0x211bef NOP

  (29) 0x211bf0 VMOVUPD	(%R12,%R14,1),%ZMM18

  (29) 0x211bf7 VMOVUPD	0x40(%R12,%R14,1),%ZMM19

  (29) 0x211bff VMOVUPD	0x40(%R15,%R14,1),%ZMM26

  (29) 0x211c07 VMOVUPD	0x80(%R12,%R14,1),%ZMM20

  (29) 0x211c0f VMOVUPD	0x80(%R15,%R14,1),%ZMM23

  (29) 0x211c17 VBROADCASTSD	(%RBX),%ZMM17

  (29) 0x211c1d VMOVAPD	%ZMM18,%ZMM21

  (29) 0x211c23 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (29) 0x211c29 VMOVAPD	%ZMM18,%ZMM22

  (29) 0x211c2f VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (29) 0x211c35 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (29) 0x211c3b VMOVUPD	(%R15,%R14,1),%ZMM18

  (29) 0x211c42 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (29) 0x211c48 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (29) 0x211c4e VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (29) 0x211c54 VMOVAPD	%ZMM18,%ZMM24

  (29) 0x211c5a VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (29) 0x211c60 VMOVAPD	%ZMM18,%ZMM25

  (29) 0x211c66 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (29) 0x211c6c VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (29) 0x211c72 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (29) 0x211c78 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (29) 0x211c7e VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (29) 0x211c84 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (29) 0x211c8a VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (29) 0x211c90 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (29) 0x211c96 VMOVAPD	%ZMM25,%ZMM17

  (29) 0x211c9c VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (29) 0x211ca2 VMOVAPD	%ZMM24,%ZMM18

  (29) 0x211ca8 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (29) 0x211cae VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (29) 0x211cb4 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (29) 0x211cba VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (29) 0x211cc0 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (29) 0x211cc6 VMOVUPD	%ZMM24,(%R15,%R14,1)

  (29) 0x211ccd VMOVUPD	%ZMM18,0x40(%R15,%R14,1)

  (29) 0x211cd5 VMOVUPD	%ZMM17,0x80(%R15,%R14,1)

  (29) 0x211cdd ADD	$0xc0,%R14

  (29) 0x211ce4 ADD	$-0x8,%R8

  (29) 0x211ce8 JNE	211bf0

(27) 0x211cee MOV	-0x40(%RBP),%R8

(27) 0x211cf2 CMP	%RCX,%RDX

(27) 0x211cf5 JE	211b10

(27) 0x211cfb TEST	$0x4,%DL

(27) 0x211cfe JNE	211d0b

(27) 0x211d00 ADD	%RCX,%R13

(27) 0x211d03 MOV	%ECX,%R14D

(27) 0x211d06 JMP	211df0

(27) 0x211d0b MOV	%RCX,%R8

(27) 0x211d0e ADD	%R13,%RCX

(27) 0x211d11 MOV	%RDX,%R14

(27) 0x211d14 AND	$-0x4,%R14

(27) 0x211d18 SAL	$0x3,%RCX

(27) 0x211d1c LEA	(%R14,%R13,1),%RAX

(27) 0x211d20 SUB	%R14,%R8

(27) 0x211d23 LEA	(%RCX,%RCX,2),%RCX

(27) 0x211d27 NOPW	(%RAX,%RAX,1)

  (30) 0x211d30 VMOVUPD	(%R12,%RCX,1),%ZMM18

  (30) 0x211d37 VMOVUPD	0x40(%R12,%RCX,1),%YMM19

  (30) 0x211d3f VMOVUPD	0x40(%R15,%RCX,1),%YMM22

  (30) 0x211d47 VBROADCASTSD	(%RBX),%YMM17

  (30) 0x211d4d VMOVAPD	%ZMM18,%ZMM20

  (30) 0x211d53 VMOVAPD	%ZMM18,%ZMM21

  (30) 0x211d59 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (30) 0x211d5f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (30) 0x211d65 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (30) 0x211d6b VMOVUPD	(%R15,%RCX,1),%ZMM19

  (30) 0x211d72 VMOVAPD	%ZMM19,%ZMM23

  (30) 0x211d78 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (30) 0x211d7e VMOVAPD	%ZMM19,%ZMM24

  (30) 0x211d84 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (30) 0x211d8a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (30) 0x211d90 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (30) 0x211d96 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (30) 0x211d9c VFMADD231PD	%YMM18,%YMM17,%YMM19

  (30) 0x211da2 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (30) 0x211da9 VMOVAPD	%ZMM17,%ZMM18

  (30) 0x211daf VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (30) 0x211db5 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (30) 0x211dbb VMOVUPD	%ZMM17,(%R15,%RCX,1)

  (30) 0x211dc2 VMOVUPD	%YMM18,0x40(%R15,%RCX,1)

  (30) 0x211dca ADD	$0x60,%RCX

  (30) 0x211dce ADD	$0x4,%R8

  (30) 0x211dd2 JNE	211d30

(27) 0x211dd8 MOV	-0x40(%RBP),%R8

(27) 0x211ddc MOV	%RAX,%R13

(27) 0x211ddf CMP	%R14,%RDX

(27) 0x211de2 JE	211b10

(27) 0x211de8 NOPL	(%RAX,%RAX,1)

(27) 0x211df0 LEA	(%R13,%R13,2),%RAX

(27) 0x211df5 SUB	%R14D,%R11D

(27) 0x211df8 LEA	0x10(,%RAX,8),%RCX

  (28) 0x211e00 VMOVSD	(%RBX),%XMM17

  (28) 0x211e06 VMOVSD	-0x10(%R12,%RCX,1),%XMM18

  (28) 0x211e0e VFMADD213SD	-0x10(%R15,%RCX,1),%XMM17,%XMM18

  (28) 0x211e16 VMOVSD	%XMM18,-0x10(%R15,%RCX,1)

  (28) 0x211e1e VMOVSD	(%RBX),%XMM17

  (28) 0x211e24 VMOVSD	-0x8(%R12,%RCX,1),%XMM18

  (28) 0x211e2c VFMADD213SD	-0x8(%R15,%RCX,1),%XMM17,%XMM18

  (28) 0x211e34 VMOVSD	%XMM18,-0x8(%R15,%RCX,1)

  (28) 0x211e3c VMOVSD	(%RBX),%XMM17

  (28) 0x211e42 VMOVSD	(%R12,%RCX,1),%XMM18

  (28) 0x211e49 VFMADD213SD	(%R15,%RCX,1),%XMM17,%XMM18

  (28) 0x211e50 VMOVSD	%XMM18,(%R15,%RCX,1)

  (28) 0x211e57 ADD	$0x18,%RCX

  (28) 0x211e5b DEC	%R11D

  (28) 0x211e5e JNE	211e00

(27) 0x211e60 JMP	211b10

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.33 to 10.33 cycles (1.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.33 to 12.08 cycles (1.43x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 17.33 to 14.17 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1012 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	83
nb uops	85
loop length	385
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.75	5.75	3.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.75	5.75	3.00	17.33	17.33	17.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.17
Dispatch	17.33
Overall L1	17.33

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	70%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	8%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	65%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

60% of peak load performance is reached (58.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.69 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 211980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R14D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 211a1f <.omp_outlined.+0x9f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
DEC %R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x4c(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x2308(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x34(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 2127e0 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %EAX,%R14D	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOVSXD -0x34(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 211a2e <.omp_outlined.+0xae>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA 0x22d9(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1
CALL 2127f0 <@plt_start@+0x190>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV (%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVAPD -0xcf79(%RIP),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcfc1(%RIP),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcfa9(%RIP),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcf51(%RIP),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xc55b(%RIP),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc865(%RIP),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc82f(%RIP),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc7f9(%RIP),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc7c3(%RIP),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc78d(%RIP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc757(%RIP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc721(%RIP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc6eb(%RIP),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc6b5(%RIP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc67f(%RIP),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc649(%RIP),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc613(%RIP),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	3	1
MOV -0x60(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %R14D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA 0x8(%RBX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R10D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV 0x78(%RCX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 211b27 <.omp_outlined.+0x1a7>	1	0.50	0	0	0	0.50	0	0	0	0	1

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 17.33 to 14.17 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1012 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	83
nb uops	85
loop length	385
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.17 cycles
front end	14.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.75	5.75	5.75	5.75	3.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.75	5.75	5.75	5.75	3.00	17.33	17.33	17.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.17
Dispatch	17.33
Overall L1	17.33

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	40%
load	70%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	8%
load	8%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	65%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

60% of peak load performance is reached (58.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.69 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 211980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RDX),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %R14D,%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 211a1f <.omp_outlined.+0x9f>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
DEC %R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0x1,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x4c(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x2308(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x34(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
CALL 2127e0 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %EAX,%R14D	1	0.50	0	0	0.50	0	0	0	0	1	0.50
MOVSXD -0x34(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %R14D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 211a2e <.omp_outlined.+0xae>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA 0x22d9(%RIP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	1
CALL 2127f0 <@plt_start@+0x190>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV (%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
VMOVAPD -0xcf79(%RIP),%YMM0	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcfc1(%RIP),%YMM1	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcfa9(%RIP),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xcf51(%RIP),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
VMOVAPD -0xc55b(%RIP),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc865(%RIP),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc82f(%RIP),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc7f9(%RIP),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc7c3(%RIP),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc78d(%RIP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc757(%RIP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc721(%RIP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc6eb(%RIP),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc6b5(%RIP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc67f(%RIP),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc649(%RIP),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	3	1
VMOVAPD -0xc613(%RIP),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	3	1
MOV -0x60(%RBP),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %R14D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA 0x8(%RBX),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV 0x18(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R10D,%ESI	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOV %RDI,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV 0x78(%RCX),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JMP 211b27 <.omp_outlined.+0x1a7>	1	0.50	0	0	0	0.50	0	0	0	0	1

Name	Coverage (%)	Time (s)
▼.omp_outlined.#0x211980–	1.32	0.15
▼Loop 27 - timestep.c:72-78 - exec–	0	0
○Loop 29 - timestep.c:74-78 - exec	1.26	0.14
○Loop 28 - timestep.c:74-78 - exec	0.05	0.01
○Loop 30 - timestep.c:74-78 - exec	0.01	0

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Matching between your function (in the source code) and the binary function

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