OV - exec - Loop 154

	Loop Id: 154	Module: exec	Source: timestep.c:88-94	Coverage: 0.38%

0x418250 MOVSXD	(%R8,%R12,4),%R13    [2]

0x418254 SAL	$0x4,%R13

0x418258 MOVDQA	%XMM0,%XMM1

0x41825c DIVSD	0x8(%R10,%R13,1),%XMM1    [4]

0x418263 MOVSD	-0x10(%R15,%R9,1),%XMM2    [1]

0x41826a MULSD	%XMM1,%XMM2

0x41826e ADDSD	-0x10(%R11,%R9,1),%XMM2    [3]

0x418275 MOVSD	%XMM2,-0x10(%R11,%R9,1)    [3]

0x41827c MOVSD	-0x8(%R15,%R9,1),%XMM2    [1]

0x418283 MULSD	%XMM1,%XMM2

0x418287 ADDSD	-0x8(%R11,%R9,1),%XMM2    [3]

0x41828e MOVSD	%XMM2,-0x8(%R11,%R9,1)    [3]

0x418295 MULSD	(%R15,%R9,1),%XMM1    [1]

0x41829b ADDSD	(%R11,%R9,1),%XMM1    [3]

0x4182a1 MOVSD	%XMM1,(%R11,%R9,1)    [3]

0x4182a7 ADD	$0x18,%R9

0x4182ab INC	%R12

0x4182ae CMP	%R12D,%EDI

0x4182b1 JNE	418250

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	P8, P9,
Function	advancePosition.extracted
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	3.42
CQA cycles if fully vectorized	1.25
Front-end cycles	3.00
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	8.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.40
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	7.69
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	13.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.46
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	P8, P9,
Function	advancePosition.extracted
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	3.42
CQA cycles if fully vectorized	1.25
Front-end cycles	3.00
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	1.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	5.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	18.00
Nb loads	8.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	1.40
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	3.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	7.69
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	13.46
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition.extracted
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 1.25 cycles (4.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.67 cycles (1.36x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 3.33 cycles (1.50x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction
3: multiply
1: divide

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	19
nb uops	18
loop length	99
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	3.67	3.67	3.67	2.00	2.00	1.50	1.50	1.50	1.50
cycles	1.25	1.25	1.00	1.00	0.50	3.67	3.67	3.67	2.00	2.00	1.50	1.50	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	3.67
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418250

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD (%R8,%R12,4),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
SAL $0x4,%R13	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVDQA %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
DIVSD 0x8(%R10,%R13,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOVSD -0x10(%R15,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD -0x10(%R11,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,-0x10(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x8(%R15,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD -0x8(%R11,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,-0x8(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MULSD (%R15,%R9,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDSD (%R11,%R9,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM1,(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 418250 <advancePosition.extracted+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	advancePosition.extracted
Source file and lines	timestep.c:88-94
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.00 to 3.33 cycles (1.50x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction
3: multiply
1: divide

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	19
nb uops	18
loop length	99
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.25	1.25	1.00	1.00	0.50	3.67	3.67	3.67	2.00	2.00	1.50	1.50	1.50	1.50
cycles	1.25	1.25	1.00	1.00	0.50	3.67	3.67	3.67	2.00	2.00	1.50	1.50	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	3.67
DIV/SQRT	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	7%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418250

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD (%R8,%R12,4),%R13	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
SAL $0x4,%R13	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVDQA %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
DIVSD 0x8(%R10,%R13,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	13	5
MOVSD -0x10(%R15,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD -0x10(%R11,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,-0x10(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x8(%R15,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD -0x8(%R11,%R9,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,-0x8(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MULSD (%R15,%R9,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADDSD (%R11,%R9,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM1,(%R11,%R9,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x18,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R12D,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 418250 <advancePosition.extracted+0xe0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code