OV - exec - Function advancePosition.extracted

	Function: advancePosition.extracted	Module: exec	Source: timestep.c:85-94	Coverage: 0.38%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x418170 PUSH	%RBP

0x418171 MOV	%RSP,%RBP

0x418174 PUSH	%R15

0x418176 PUSH	%R14

0x418178 PUSH	%R13

0x41817a PUSH	%R12

0x41817c PUSH	%RBX

0x41817d SUB	$0x18,%RSP

0x418181 MOV	%RCX,%R15

0x418184 MOV	%RDX,%RBX

0x418187 MOVL	$0,-0x38(%RBP)

0x41818e MOV	(%RDI),%R14D

0x418191 MOVL	$0,-0x30(%RBP)

0x418198 MOV	%R9D,-0x2c(%RBP)

0x41819c MOVL	$0x1,-0x34(%RBP)

0x4181a3 SUB	$0x8,%RSP

0x4181a7 LEA	-0x34(%RBP),%RAX

0x4181ab LEA	-0x38(%RBP),%RCX

0x4181af LEA	-0x30(%RBP),%R8

0x4181b3 LEA	-0x2c(%RBP),%R9

0x4181b7 MOV	$0x438a50,%EDI

0x4181bc MOV	%R14D,%ESI

0x4181bf MOV	$0x22,%EDX

0x4181c4 PUSH	$0x1

0x4181c6 PUSH	$0x1

0x4181c8 PUSH	%RAX

0x4181c9 CALL	405320 <__kmpc_for_static_init_4@plt>

0x4181ce ADD	$0x20,%RSP

0x4181d2 MOV	-0x30(%RBP),%EAX

0x4181d5 MOV	-0x2c(%RBP),%ECX

0x4181d8 CMP	%ECX,%EAX

0x4181da JBE	4181f7

0x4181dc MOV	$0x438a70,%EDI

0x4181e1 MOV	%R14D,%ESI

0x4181e4 ADD	$0x18,%RSP

0x4181e8 POP	%RBX

0x4181e9 POP	%R12

0x4181eb POP	%R13

0x4181ed POP	%R14

0x4181ef POP	%R15

0x4181f1 POP	%RBP

0x4181f2 JMP	405150

0x4181f7 MOVQ	%R15,%XMM0

0x4181fc MOV	0x18(%RBX),%RDX

0x418200 MOV	0x78(%RDX),%RDX

0x418204 MOV	%EAX,%ESI

0x418206 SAL	$0x6,%ESI

0x418209 INC	%RCX

0x41820c JMP	41821b

0x41820e XCHG	%AX,%AX

(153) 0x418210 INC	%RAX

(153) 0x418213 ADD	$0x40,%ESI

(153) 0x418216 CMP	%RCX,%RAX

(153) 0x418219 JE	4181dc

(153) 0x41821b MOV	(%RDX,%RAX,4),%EDI

(153) 0x41821e TEST	%EDI,%EDI

(153) 0x418220 JLE	418210

(153) 0x418222 MOV	%ESI,%R8D

(153) 0x418225 LEA	(%R8,%R8,2),%R9

(153) 0x418229 LEA	0x10(,%R9,8),%R9

(153) 0x418231 SAL	$0x2,%R8

(153) 0x418235 MOV	0x20(%RBX),%R12

(153) 0x418239 MOV	0x28(%RBX),%R10

(153) 0x41823d MOV	0x18(%R12),%R11

(153) 0x418242 MOV	0x20(%R12),%R15

(153) 0x418247 ADD	0x10(%R12),%R8

(153) 0x41824c XOR	%R12D,%R12D

(153) 0x41824f NOP

  (154) 0x418250 MOVSXD	(%R8,%R12,4),%R13

  (154) 0x418254 SAL	$0x4,%R13

  (154) 0x418258 MOVDQA	%XMM0,%XMM1

  (154) 0x41825c DIVSD	0x8(%R10,%R13,1),%XMM1

  (154) 0x418263 MOVSD	-0x10(%R15,%R9,1),%XMM2

  (154) 0x41826a MULSD	%XMM1,%XMM2

  (154) 0x41826e ADDSD	-0x10(%R11,%R9,1),%XMM2

  (154) 0x418275 MOVSD	%XMM2,-0x10(%R11,%R9,1)

  (154) 0x41827c MOVSD	-0x8(%R15,%R9,1),%XMM2

  (154) 0x418283 MULSD	%XMM1,%XMM2

  (154) 0x418287 ADDSD	-0x8(%R11,%R9,1),%XMM2

  (154) 0x41828e MOVSD	%XMM2,-0x8(%R11,%R9,1)

  (154) 0x418295 MULSD	(%R15,%R9,1),%XMM1

  (154) 0x41829b ADDSD	(%R11,%R9,1),%XMM1

  (154) 0x4182a1 MOVSD	%XMM1,(%R11,%R9,1)

  (154) 0x4182a7 ADD	$0x18,%R9

  (154) 0x4182ab INC	%R12

  (154) 0x4182ae CMP	%R12D,%EDI

  (154) 0x4182b1 JNE	418250

(153) 0x4182b3 JMP	418210

0x4182b8 NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 0.83 cycles (10.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.57 cycles (14.84x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	51
nb uops	51
loop length	168
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00
cycles	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (3.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.88 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 4.00 cycles (2.13x speedup).

ASM code

In the binary file, the address of the function is: 418170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVL $0x1,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x438a50,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 4181f7 <advancePosition.extracted+0x87>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438a70,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	6	1
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 41821b <advancePosition.extracted+0xab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 0.83 cycles (10.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	51
nb uops	51
loop length	168
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00
cycles	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	4.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (3.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.88 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 418170

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVL $0x1,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x2c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x438a50,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 4181f7 <advancePosition.extracted+0x87>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438a70,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	6	1
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 41821b <advancePosition.extracted+0xab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼advancePosition.extracted–	0.38	0.04
▼Loop 153 - timestep.c:85-94 - exec–	0	0
○Loop 154 - timestep.c:88-94 - exec	0.38	0.04

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