OV - exec - Function advanceVelocity.extracted

	Function: advanceVelocity.extracted	Module: exec	Source: timestep.c:71-78	Coverage: 0.68%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x418040 PUSH	%RBP

0x418041 MOV	%RSP,%RBP

0x418044 PUSH	%R15

0x418046 PUSH	%R14

0x418048 PUSH	%RBX

0x418049 SUB	$0x18,%RSP

0x41804d MOV	%RCX,%R15

0x418050 MOV	%RDX,%RBX

0x418053 MOVL	$0,-0x28(%RBP)

0x41805a MOV	(%RDI),%R14D

0x41805d MOVL	$0,-0x20(%RBP)

0x418064 MOV	%R9D,-0x1c(%RBP)

0x418068 MOVL	$0x1,-0x24(%RBP)

0x41806f SUB	$0x8,%RSP

0x418073 LEA	-0x24(%RBP),%RAX

0x418077 LEA	-0x28(%RBP),%RCX

0x41807b LEA	-0x20(%RBP),%R8

0x41807f LEA	-0x1c(%RBP),%R9

0x418083 MOV	$0x4389f0,%EDI

0x418088 MOV	%R14D,%ESI

0x41808b MOV	$0x22,%EDX

0x418090 PUSH	$0x1

0x418092 PUSH	$0x1

0x418094 PUSH	%RAX

0x418095 CALL	405320 <__kmpc_for_static_init_4@plt>

0x41809a ADD	$0x20,%RSP

0x41809e MOV	-0x20(%RBP),%EAX

0x4180a1 MOV	-0x1c(%RBP),%ECX

0x4180a4 CMP	%ECX,%EAX

0x4180a6 JBE	4180bf

0x4180a8 MOV	$0x438a10,%EDI

0x4180ad MOV	%R14D,%ESI

0x4180b0 ADD	$0x18,%RSP

0x4180b4 POP	%RBX

0x4180b5 POP	%R14

0x4180b7 POP	%R15

0x4180b9 POP	%RBP

0x4180ba JMP	405150

0x4180bf MOVQ	%R15,%XMM0

0x4180c4 MOV	0x18(%RBX),%RDX

0x4180c8 MOV	0x78(%RDX),%RDX

0x4180cc MOV	%EAX,%ESI

0x4180ce SAL	$0x6,%ESI

0x4180d1 INC	%RCX

0x4180d4 JMP	4180eb

0x4180d6 NOPW	%CS:(%RAX,%RAX,1)

(151) 0x4180e0 INC	%RAX

(151) 0x4180e3 ADD	$0x40,%ESI

(151) 0x4180e6 CMP	%RCX,%RAX

(151) 0x4180e9 JE	4180a8

(151) 0x4180eb MOV	(%RDX,%RAX,4),%EDI

(151) 0x4180ee TEST	%EDI,%EDI

(151) 0x4180f0 JLE	4180e0

(151) 0x4180f2 MOV	%ESI,%R8D

(151) 0x4180f5 LEA	(%R8,%R8,2),%R8

(151) 0x4180f9 LEA	0x10(,%R8,8),%R8

(151) 0x418101 MOV	0x20(%RBX),%R10

(151) 0x418105 MOV	0x20(%R10),%R9

(151) 0x418109 MOV	0x28(%R10),%R10

(151) 0x41810d NOPL	(%RAX)

  (152) 0x418110 MOVSD	-0x10(%R10,%R8,1),%XMM1

  (152) 0x418117 MULSD	%XMM0,%XMM1

  (152) 0x41811b ADDSD	-0x10(%R9,%R8,1),%XMM1

  (152) 0x418122 MOVSD	%XMM1,-0x10(%R9,%R8,1)

  (152) 0x418129 MOVSD	-0x8(%R10,%R8,1),%XMM1

  (152) 0x418130 MULSD	%XMM0,%XMM1

  (152) 0x418134 ADDSD	-0x8(%R9,%R8,1),%XMM1

  (152) 0x41813b MOVSD	%XMM1,-0x8(%R9,%R8,1)

  (152) 0x418142 MOVSD	(%R10,%R8,1),%XMM1

  (152) 0x418148 MULSD	%XMM0,%XMM1

  (152) 0x41814c ADDSD	(%R9,%R8,1),%XMM1

  (152) 0x418152 MOVSD	%XMM1,(%R9,%R8,1)

  (152) 0x418158 ADD	$0x18,%R8

  (152) 0x41815c DEC	%EDI

  (152) 0x41815e JNE	418110

(151) 0x418160 JMP	4180e0

0x418165 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.83 to 0.83 cycles (9.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.83 to 0.53 cycles (14.75x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	47
nb uops	47
loop length	171
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00
cycles	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	4.00
Overall L1	7.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.83 cycles. At this rate:

3% of peak load performance is reached (3.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.83 to 4.00 cycles (1.96x speedup).

ASM code

In the binary file, the address of the function is: 418040

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R9D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVL $0x1,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x28(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x4389f0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x20(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x1c(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 4180bf <advanceVelocity.extracted+0x7f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438a10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	6	1
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 4180eb <advanceVelocity.extracted+0xab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.83 to 0.83 cycles (9.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	47
nb uops	47
loop length	171
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.83 cycles
front end	7.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00
cycles	4.00	4.00	4.00	4.00	2.00	3.33	3.33	3.33	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.83
Dispatch	4.00
Overall L1	7.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.83 cycles. At this rate:

3% of peak load performance is reached (3.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.04 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 418040

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV %R9D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVL $0x1,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x28(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV $0x4389f0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV -0x20(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV -0x1c(%RBP),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
CMP %ECX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JBE 4180bf <advanceVelocity.extracted+0x7f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438a10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
MOVQ %R15,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	6	1
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JMP 4180eb <advanceVelocity.extracted+0xab>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼advanceVelocity.extracted–	0.68	0.07
▼Loop 151 - timestep.c:71-78 - exec–	0	0
○Loop 152 - timestep.c:74-78 - exec	0.68	0.07

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code