OV - exec - Function putAtomInBox.A

	Function: putAtomInBox.A	Module: exec	Source: linkCells.c:173-378 [...]	Coverage: 0.11%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 173 - 378

--------------------------------------------------------------------------------

173: {

174:    real_t xyz[3] = {x,y,z};

175:

176:    // Find correct box.

177:    int iBox = getBoxFromCoord(boxes, xyz);

178:    int iOff = iBox*MAXATOMS;

179:    iOff += boxes->nAtoms[iBox];

180:

181:    // assign values to array elements

182:    if (iBox < boxes->nLocalBoxes)

183:       atoms->nLocal++;

184:    boxes->nAtoms[iBox]++;

185:    atoms->gid[iOff] = gid;

186:    atoms->iSpecies[iOff] = iType;

187:

188:    atoms->r[iOff][0] = x;

189:    atoms->r[iOff][1] = y;

190:    atoms->r[iOff][2] = z;

191:

192:    atoms->p[iOff][0] = px;

193:    atoms->p[iOff][1] = py;

194:    atoms->p[iOff][2] = pz;

195: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

0x40f650 PUSH	%RBP

0x40f651 MOV	%RSP,%RBP

0x40f654 PUSH	%R15

0x40f656 PUSH	%R14

0x40f658 PUSH	%R12

0x40f65a PUSH	%RBX

0x40f65b SUB	$0x70,%RSP

0x40f65f MOVSD	%XMM5,-0x58(%RBP)

0x40f664 MOVSD	%XMM4,-0x50(%RBP)

0x40f669 MOVSD	%XMM3,-0x48(%RBP)

0x40f66e MOVSD	%XMM0,-0x28(%RBP)

0x40f673 MOV	%ECX,%R14D

0x40f676 MOV	%EDX,%R15D

0x40f679 MOV	%RSI,%RBX

0x40f67c MOV	%RDI,%R12

0x40f67f MOVAPD	%XMM1,-0x70(%RBP)

0x40f684 MOVAPD	%XMM1,%XMM3

0x40f688 MOVAPD	%XMM2,-0x80(%RBP)

0x40f68d UNPCKLPD	%XMM2,%XMM3

0x40f691 MOVUPD	0x20(%RDI),%XMM1

0x40f696 SUBPD	%XMM1,%XMM3

0x40f69a MOVUPD	0x68(%RDI),%XMM0

0x40f69f MULPD	%XMM3,%XMM0

0x40f6a3 MOVAPD	%XMM0,-0x90(%RBP)

0x40f6ab CALL	418d00 <floor>

0x40f6b0 MOVAPD	%XMM0,-0x40(%RBP)

0x40f6b5 MOVAPD	-0x90(%RBP),%XMM0

0x40f6bd UNPCKHPD	%XMM0,%XMM0

0x40f6c1 CALL	418d00 <floor>

0x40f6c6 MOVAPD	-0x40(%RBP),%XMM1

0x40f6cb UNPCKLPD	%XMM0,%XMM1

0x40f6cf MOVSD	-0x28(%RBP),%XMM0

0x40f6d4 CVTTPD2DQ	%XMM1,%XMM1

0x40f6d8 UCOMISD	0x30(%R12),%XMM0

0x40f6df JAE	40f710

0x40f6e1 SUBSD	0x18(%R12),%XMM0

0x40f6e8 MULSD	0x60(%R12),%XMM0

0x40f6ef MOVAPD	%XMM1,-0x40(%RBP)

0x40f6f4 CALL	418d00 <floor>

0x40f6f9 MOVAPD	-0x40(%RBP),%XMM1

0x40f6fe CVTTSD2SI	%XMM0,%EAX

0x40f702 MOV	(%R12),%ECX

0x40f706 LEA	-0x1(%RCX),%ESI

0x40f709 CMP	%EAX,%ECX

0x40f70b CMOVNE	%EAX,%ESI

0x40f70e JMP	40f714

0x40f710 MOV	(%R12),%ESI

0x40f714 MOV	0x4(%R12),%RAX

0x40f719 MOVQ	%RAX,%XMM0

0x40f71e LEA	-0x1(%RAX),%ECX

0x40f721 PCMPEQD	%XMM1,%XMM0

0x40f725 PSHUFD	$0x50,%XMM0,%XMM0

0x40f72a MOVMSKPD	%XMM0,%EDI

0x40f72e MOVD	%XMM1,%EDX

0x40f732 TEST	$0x1,%DIL

0x40f736 CMOVNE	%ECX,%EDX

0x40f739 MOVAPD	-0x70(%RBP),%XMM0

0x40f73e UCOMISD	0x38(%R12),%XMM0

0x40f745 CMOVAE	%EAX,%EDX

0x40f748 SHR	$0x20,%RAX

0x40f74c LEA	-0x1(%RAX),%R8D

0x40f750 PSHUFD	$0x55,%XMM1,%XMM0

0x40f755 MOVD	%XMM0,%ECX

0x40f759 TEST	$0x2,%DIL

0x40f75d CMOVNE	%R8D,%ECX

0x40f761 MOVAPD	-0x80(%RBP),%XMM0

0x40f766 UCOMISD	0x40(%R12),%XMM0

0x40f76d CMOVAE	%EAX,%ECX

0x40f770 MOV	%R12,%RDI

0x40f773 CALL	40f540 <getBoxFromTuple.A>

0x40f778 MOV	0x78(%R12),%RCX

0x40f77d MOV	%EAX,%EDX

0x40f77f MOV	(%RCX,%RDX,4),%ESI

0x40f782 MOV	%ESI,%EDI

0x40f784 CMP	0xc(%R12),%EAX

0x40f789 JGE	40f790

0x40f78b INCL	(%RBX)

0x40f78d MOV	(%RCX,%RDX,4),%EDI

0x40f790 MOV	%EDX,%EAX

0x40f792 SAL	$0x6,%EAX

0x40f795 ADD	%EAX,%ESI

0x40f797 INC	%EDI

0x40f799 MOV	%EDI,(%RCX,%RDX,4)

0x40f79c MOV	0x8(%RBX),%RAX

0x40f7a0 MOVSXD	%ESI,%RCX

0x40f7a3 MOV	%R15D,(%RAX,%RCX,4)

0x40f7a7 MOV	0x10(%RBX),%RAX

0x40f7ab MOV	%R14D,(%RAX,%RCX,4)

0x40f7af MOV	0x18(%RBX),%RAX

0x40f7b3 SAL	$0x3,%RCX

0x40f7b7 LEA	(%RCX,%RCX,2),%RCX

0x40f7bb MOVSD	-0x28(%RBP),%XMM0

0x40f7c0 MOVSD	%XMM0,(%RAX,%RCX,1)

0x40f7c5 MOVAPS	-0x70(%RBP),%XMM0

0x40f7c9 MOVSD	%XMM0,0x8(%RAX,%RCX,1)

0x40f7cf MOVAPS	-0x80(%RBP),%XMM0

0x40f7d3 MOVSD	%XMM0,0x10(%RAX,%RCX,1)

0x40f7d9 MOV	0x20(%RBX),%RAX

0x40f7dd MOVSD	-0x48(%RBP),%XMM0

0x40f7e2 MOVSD	%XMM0,(%RAX,%RCX,1)

0x40f7e7 MOVSD	-0x50(%RBP),%XMM0

0x40f7ec MOVSD	%XMM0,0x8(%RAX,%RCX,1)

0x40f7f2 MOVSD	-0x58(%RBP),%XMM0

0x40f7f7 MOVSD	%XMM0,0x10(%RAX,%RCX,1)

0x40f7fd ADD	$0x70,%RSP

0x40f801 POP	%RBX

0x40f802 POP	%R12

0x40f804 POP	%R14

0x40f806 POP	%R15

0x40f808 POP	%RBP

0x40f809 RET

0x40f80a NOPW	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:173-378
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:173-195,352-365,371,378.

This function has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.75 to 3.75 cycles (5.00x speedup).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

41% of SSE/AVX loads are used in vector version.
24% of SSE/AVX stores are used in vector version.
41% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX multiply instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

floor: 2.50 occurrences
getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTTSD2SI: 1 occurrences
INC: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
CVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

2.50: addition or subtraction
2.50: multiply

The binary function is loading 272 bytes (34 double precision FP elements). The binary function is storing 166 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	104
nb uops	112.50
loop length	414
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.88	5.88	5.63	5.63	4.00	16.17	16.17	16.17	2.75	3.92	4.00	3.83	10.50	10.50
cycles	5.88	5.88	5.63	5.63	4.00	16.17	16.17	16.17	2.75	3.92	4.00	3.83	10.50	10.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.75
Dispatch	16.17
Overall L1	18.75

Vectorization ratios

INT

all	18%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	44%
load	48%
store	30%
mul	75%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	37%
load	41%
store	24%
mul	75%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	18%
store	16%
mul	21%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	16%
store	14%
mul	21%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.75 cycles. At this rate:

15% of peak load performance is reached (14.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.86 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 11.33 cycles (1.76x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

36% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

floor: 3 occurrences
getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTTSD2SI: 1 occurrences
INC: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
CVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 292 bytes (36 double precision FP elements). The binary function is storing 176 bytes (22 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	110
nb uops	120
loop length	438
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.00 cycles
front end	20.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.50	6.50	6.25	6.25	4.50	17.33	17.33	17.33	3.00	4.33	4.50	4.17	11.00	11.00
cycles	6.50	6.50	6.25	6.25	4.50	17.33	17.33	17.33	3.00	4.33	4.50	4.17	11.00	11.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.00
Dispatch	17.33
Overall L1	20.00

Vectorization ratios

INT

all	17%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	44%
load	47%
store	33%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	36%
load	40%
store	26%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	18%
store	16%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	16%
store	14%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

15% of peak load performance is reached (14.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 17.33 cycles (1.15x speedup).

ASM code

In the binary file, the address of the function is: 40f650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM2,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVUPD 0x20(%RDI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD 0x68(%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM0,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x90(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
CVTTPD2DQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD 0x30(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40f710 <putAtomInBox.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SUBSD 0x18(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULSD 0x60(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
CVTTSD2SI %XMM0,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	9	1
MOV (%R12),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x1(%RCX),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %EAX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
JMP 40f714 <putAtomInBox.A+0xc4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
LEA -0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PCMPEQD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM0,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
MOVD %XMM1,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x38(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PSHUFD $0x55,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x2,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x40(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP 0xc(%R12),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f790 <putAtomInBox.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INCL (%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%RCX,%RDX,4),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x48(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.50 to 11.33 cycles (1.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
27% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
28% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

floor: 3 occurrences
getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTTSD2SI: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
CVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 284 bytes (35 double precision FP elements). The binary function is storing 172 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	108
nb uops	117
loop length	433
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.50 cycles
front end	19.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.00	6.00	4.50	16.67	16.67	16.67	3.00	4.33	4.50	4.17	11.00	11.00
cycles	6.25	6.25	6.00	6.00	4.50	16.67	16.67	16.67	3.00	4.33	4.50	4.17	11.00	11.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.50
Dispatch	16.67
Overall L1	19.50

Vectorization ratios

INT

all	18%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	44%
load	47%
store	33%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	37%
load	42%
store	27%
mul	50%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	18%
load	18%
store	16%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	17%
store	14%
mul	18%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.50 cycles. At this rate:

15% of peak load performance is reached (14.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.82 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM2,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVUPD 0x20(%RDI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD 0x68(%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM0,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x90(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
CVTTPD2DQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD 0x30(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40f710 <putAtomInBox.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
SUBSD 0x18(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULSD 0x60(%R12),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
CVTTSD2SI %XMM0,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	9	1
MOV (%R12),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x1(%RCX),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EAX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %EAX,%ESI	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
JMP 40f714 <putAtomInBox.A+0xc4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
LEA -0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PCMPEQD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM0,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
MOVD %XMM1,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x38(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PSHUFD $0x55,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x2,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x40(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP 0xc(%R12),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f790 <putAtomInBox.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x48(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 10.00 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

floor: 2 occurrences
getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 260 bytes (32 double precision FP elements). The binary function is storing 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	100
nb uops	108
loop length	395
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.50	5.50	5.25	5.25	3.50	15.67	15.67	15.67	2.50	3.50	3.50	3.50	10.00	10.00
cycles	5.50	5.50	5.25	5.25	3.50	15.67	15.67	15.67	2.50	3.50	3.50	3.50	10.00	10.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	15.67
Overall L1	18.00

Vectorization ratios

INT

all	18%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	44%
load	50%
store	28%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	37%
load	40%
store	22%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	18%
load	18%
store	16%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	16%
store	13%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

15% of peak load performance is reached (14.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.89 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM2,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVUPD 0x20(%RDI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD 0x68(%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM0,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x90(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
CVTTPD2DQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD 0x30(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40f710 <putAtomInBox.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
LEA -0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PCMPEQD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM0,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
MOVD %XMM1,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x38(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PSHUFD $0x55,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x2,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x40(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP 0xc(%R12),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f790 <putAtomInBox.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
INCL (%RBX)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV (%RCX,%RDX,4),%EDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x48(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.50 to 10.00 cycles (1.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
23% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

floor: 2 occurrences
getBoxFromTuple: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 252 bytes (31 double precision FP elements). The binary function is storing 156 bytes (19 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	105
loop length	390
used x86 registers	12
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	8
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	5.25	5.25	5.00	5.00	3.50	15.00	15.00	15.00	2.50	3.50	3.50	3.50	10.00	10.00
cycles	5.25	5.25	5.00	5.00	3.50	15.00	15.00	15.00	2.50	3.50	3.50	3.50	10.00	10.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.50
Dispatch	15.00
Overall L1	17.50

Vectorization ratios

INT

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	44%
load	50%
store	28%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	37%
load	42%
store	23%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	18%
load	18%
store	16%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	15%
load	16%
store	14%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.50 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD %XMM5,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM1,-0x70(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD %XMM2,-0x80(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
UNPCKLPD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVUPD 0x20(%RDI),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD 0x68(%RDI),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM0,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x90(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD -0x40(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
CVTTPD2DQ %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD 0x30(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40f710 <putAtomInBox.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x4(%R12),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
LEA -0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PCMPEQD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM0,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
MOVD %XMM1,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x1,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x38(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x1(%RAX),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PSHUFD $0x55,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
TEST $0x2,%DIL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVNE %R8D,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVAPD -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UCOMISD 0x40(%R12),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV 0x78(%R12),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV (%RCX,%RDX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP 0xc(%R12),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f790 <putAtomInBox.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD %EAX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,(%RCX,%RDX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x8(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD %ESI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R15D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R14D,(%RAX,%RCX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
SAL $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD -0x28(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x70(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVAPS -0x80(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD -0x48(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x8(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,0x10(%RAX,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x70,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
○putAtomInBox.A	0.11	0.01

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CALL instructions

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Complex instructions

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Vector unaligned load/store instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

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