OV - exec - Loop 97

	Loop Id: 97	Module: exec	Source: timestep.c:74-78	Coverage: 0.86%

0x40f61b VMOVSD	(%RCX),%XMM7    [3]

0x40f61f VFMADD213SD	(%RSI),%XMM0,%XMM7    [4]

0x40f624 ADD	$0xc0,%RSI

0x40f62b ADD	$0xc0,%RCX

0x40f632 VMOVSD	%XMM7,-0xc0(%RSI)    [2]

0x40f63a VMOVSD	-0xb8(%RCX),%XMM8    [1]

0x40f642 VFMADD213SD	-0xb8(%RSI),%XMM0,%XMM8    [2]

0x40f64b VMOVSD	%XMM8,-0xb8(%RSI)    [2]

0x40f653 VMOVSD	-0xb0(%RCX),%XMM9    [1]

0x40f65b VFMADD213SD	-0xb0(%RSI),%XMM0,%XMM9    [2]

0x40f664 VMOVSD	%XMM9,-0xb0(%RSI)    [2]

0x40f66c VMOVSD	-0xa8(%RCX),%XMM10    [1]

0x40f674 VFMADD213SD	-0xa8(%RSI),%XMM0,%XMM10    [2]

0x40f67d VMOVSD	%XMM10,-0xa8(%RSI)    [2]

0x40f685 VMOVSD	-0xa0(%RCX),%XMM11    [1]

0x40f68d VFMADD213SD	-0xa0(%RSI),%XMM0,%XMM11    [2]

0x40f696 VMOVSD	%XMM11,-0xa0(%RSI)    [2]

0x40f69e VMOVSD	-0x98(%RCX),%XMM12    [1]

0x40f6a6 VFMADD213SD	-0x98(%RSI),%XMM0,%XMM12    [2]

0x40f6af VMOVSD	%XMM12,-0x98(%RSI)    [2]

0x40f6b7 VMOVSD	-0x90(%RCX),%XMM13    [1]

0x40f6bf VFMADD213SD	-0x90(%RSI),%XMM0,%XMM13    [2]

0x40f6c8 VMOVSD	%XMM13,-0x90(%RSI)    [2]

0x40f6d0 VMOVSD	-0x88(%RCX),%XMM14    [1]

0x40f6d8 VFMADD213SD	-0x88(%RSI),%XMM0,%XMM14    [2]

0x40f6e1 VMOVSD	%XMM14,-0x88(%RSI)    [2]

0x40f6e9 VMOVSD	-0x80(%RCX),%XMM15    [1]

0x40f6ee VFMADD213SD	-0x80(%RSI),%XMM0,%XMM15    [2]

0x40f6f4 VMOVSD	%XMM15,-0x80(%RSI)    [2]

0x40f6f9 VMOVSD	-0x78(%RCX),%XMM1    [1]

0x40f6fe VFMADD213SD	-0x78(%RSI),%XMM0,%XMM1    [2]

0x40f704 VMOVSD	%XMM1,-0x78(%RSI)    [2]

0x40f709 VMOVSD	-0x70(%RCX),%XMM2    [1]

0x40f70e VFMADD213SD	-0x70(%RSI),%XMM0,%XMM2    [2]

0x40f714 VMOVSD	%XMM2,-0x70(%RSI)    [2]

0x40f719 VMOVSD	-0x68(%RCX),%XMM3    [1]

0x40f71e VFMADD213SD	-0x68(%RSI),%XMM0,%XMM3    [2]

0x40f724 VMOVSD	%XMM3,-0x68(%RSI)    [2]

0x40f729 VMOVSD	-0x60(%RCX),%XMM4    [1]

0x40f72e VFMADD213SD	-0x60(%RSI),%XMM0,%XMM4    [2]

0x40f734 VMOVSD	%XMM4,-0x60(%RSI)    [2]

0x40f739 VMOVSD	-0x58(%RCX),%XMM5    [1]

0x40f73e VFMADD213SD	-0x58(%RSI),%XMM0,%XMM5    [2]

0x40f744 VMOVSD	%XMM5,-0x58(%RSI)    [2]

0x40f749 VMOVSD	-0x50(%RCX),%XMM6    [1]

0x40f74e VFMADD213SD	-0x50(%RSI),%XMM0,%XMM6    [2]

0x40f754 VMOVSD	%XMM6,-0x50(%RSI)    [2]

0x40f759 VMOVSD	-0x48(%RCX),%XMM7    [1]

0x40f75e VFMADD213SD	-0x48(%RSI),%XMM0,%XMM7    [2]

0x40f764 VMOVSD	%XMM7,-0x48(%RSI)    [2]

0x40f769 VMOVSD	-0x40(%RCX),%XMM8    [1]

0x40f76e VFMADD213SD	-0x40(%RSI),%XMM0,%XMM8    [2]

0x40f774 VMOVSD	%XMM8,-0x40(%RSI)    [2]

0x40f779 VMOVSD	-0x38(%RCX),%XMM9    [1]

0x40f77e VFMADD213SD	-0x38(%RSI),%XMM0,%XMM9    [2]

0x40f784 VMOVSD	%XMM9,-0x38(%RSI)    [2]

0x40f789 VMOVSD	-0x30(%RCX),%XMM10    [1]

0x40f78e VFMADD213SD	-0x30(%RSI),%XMM0,%XMM10    [2]

0x40f794 VMOVSD	%XMM10,-0x30(%RSI)    [2]

0x40f799 VMOVSD	-0x28(%RCX),%XMM11    [1]

0x40f79e VFMADD213SD	-0x28(%RSI),%XMM0,%XMM11    [2]

0x40f7a4 VMOVSD	%XMM11,-0x28(%RSI)    [2]

0x40f7a9 VMOVSD	-0x20(%RCX),%XMM12    [1]

0x40f7ae VFMADD213SD	-0x20(%RSI),%XMM0,%XMM12    [2]

0x40f7b4 VMOVSD	%XMM12,-0x20(%RSI)    [2]

0x40f7b9 VMOVSD	-0x18(%RCX),%XMM13    [1]

0x40f7be VFMADD213SD	-0x18(%RSI),%XMM0,%XMM13    [2]

0x40f7c4 VMOVSD	%XMM13,-0x18(%RSI)    [2]

0x40f7c9 VMOVSD	-0x10(%RCX),%XMM14    [1]

0x40f7ce VFMADD213SD	-0x10(%RSI),%XMM0,%XMM14    [2]

0x40f7d4 VMOVSD	%XMM14,-0x10(%RSI)    [2]

0x40f7d9 VMOVSD	-0x8(%RCX),%XMM15    [1]

0x40f7de VFMADD213SD	-0x8(%RSI),%XMM0,%XMM15    [2]

0x40f7e4 VMOVSD	%XMM15,-0x8(%RSI)    [2]

0x40f7e9 CMP	%RSI,%RDX

0x40f7ec JNE	40f61b

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.92
Bottlenecks	P5, P6, P7,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	5.00
Front-end cycles	12.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	75.00
Nb loads	48.00
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.92
Bottlenecks	P5, P6, P7,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	5.00
Front-end cycles	12.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	12.00
P12 cycles	12.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	75.00
Nb loads	48.00
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 5.00 cycles (4.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 12.50 cycles (1.92x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 24 FMA (fused multiply-add) operations.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	76
nb uops	75
loop length	471
used x86 registers	3
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	12.00	12.00	0.00	0.00	12.00	12.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	12.00	12.00	0.00	0.00	12.00	12.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Dispatch	24.00
Data deps.	1.00
Overall L1	24.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f61b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0xc0,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0xc0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM7,-0xc0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xb8(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xb8(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0xb8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xb0(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xb0(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0xb0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xa8(%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xa8(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0xa8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xa0(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xa0(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0xa0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x98(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x98(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x98(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x90(%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x90(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x90(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x88(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x88(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x88(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x80(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x80(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x80(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x78(%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x78(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,-0x78(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x70(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x70(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x70(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x68(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x68(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x68(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x60(%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x60(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,-0x60(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x58(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x58(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x58(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x50(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x50(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x50(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x48(%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x48(%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM7,-0x48(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x40(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x40(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x38(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x38(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x38(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x30(%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x30(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0x30(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x28(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x28(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0x28(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x20(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x20(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x20(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x18(%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x18(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 40f61b <advanceVelocity._omp_fn.0+0x25b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 24.00 to 5.00 cycles (4.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 12.50 cycles (1.92x speedup).

Workaround

Read less array elements All SSE and/or AVX registers are used: in that case, try to relax register pressure by reducing the unroll factor or splitting your loop
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

FMA

Detected 24 FMA (fused multiply-add) operations.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	76
nb uops	75
loop length	471
used x86 registers	3
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	12.00	12.00	0.00	0.00	12.00	12.00
cycles	0.75	0.75	0.50	0.50	0.50	24.00	24.00	24.00	12.00	12.00	0.00	0.00	12.00	12.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Dispatch	24.00
Data deps.	1.00
Overall L1	24.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (8.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f61b

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP4	FP5	Latency	Recip. throughput
VMOVSD (%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD (%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
ADD $0xc0,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0xc0,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM7,-0xc0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xb8(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xb8(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0xb8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xb0(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xb0(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0xb0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xa8(%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xa8(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0xa8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0xa0(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0xa0(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0xa0(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x98(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x98(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x98(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x90(%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x90(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x90(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x88(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x88(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x88(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x80(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x80(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x80(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x78(%RCX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x78(%RSI),%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM1,-0x78(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x70(%RCX),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x70(%RSI),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM2,-0x70(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x68(%RCX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x68(%RSI),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM3,-0x68(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x60(%RCX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x60(%RSI),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM4,-0x60(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x58(%RCX),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x58(%RSI),%XMM0,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM5,-0x58(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x50(%RCX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x50(%RSI),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM6,-0x50(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x48(%RCX),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x48(%RSI),%XMM0,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM7,-0x48(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x40(%RCX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x40(%RSI),%XMM0,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM8,-0x40(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x38(%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x38(%RSI),%XMM0,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM9,-0x38(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x30(%RCX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x30(%RSI),%XMM0,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM10,-0x30(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x28(%RCX),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x28(%RSI),%XMM0,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM11,-0x28(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x20(%RCX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x20(%RSI),%XMM0,%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM12,-0x20(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x18(%RCX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x18(%RSI),%XMM0,%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM13,-0x18(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x10(%RCX),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x10(%RSI),%XMM0,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM14,-0x10(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
VMOVSD -0x8(%RCX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
VFMADD213SD -0x8(%RSI),%XMM0,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	4	0.50
VMOVSD %XMM15,-0x8(%RSI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
CMP %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JNE 40f61b <advanceVelocity._omp_fn.0+0x25b>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code