OV - exec - Loop 78

	Loop Id: 78	Module: exec	Source: linkCells.c:211-373 [...]	Coverage: 0.71%

0x40b230 MOVSXD	%R15D,%R8

0x40b233 MOV	%EDI,%EAX

0x40b235 LEA	(%R8,%R8,2),%R9

0x40b239 LEA	(%R10,%R9,8),%R11

0x40b23d VMOVSD	(%R11),%XMM2    [3]

0x40b242 VCOMISD	0x30(%RBX),%XMM2    [1]

0x40b247 VMOVSD	0x8(%R11),%XMM1    [3]

0x40b24d VMOVSD	0x10(%R11),%XMM0    [3]

0x40b253 JAE	40b272

0x40b255 VSUBSD	%XMM8,%XMM2,%XMM9

0x40b25a XOR	%EDX,%EDX

0x40b25c VMULSD	%XMM7,%XMM9,%XMM10

0x40b260 VROUNDSD	$0x9,%XMM10,%XMM10,%XMM10

0x40b266 VCVTTSD2SI	%XMM10,%EAX

0x40b26b CMP	%EDI,%EAX

0x40b26d SETE	%DL

0x40b270 SUB	%EDX,%EAX

0x40b272 VCOMISD	0x38(%RBX),%XMM1    [1]

0x40b277 MOV	%ECX,%R8D

0x40b27a JAE	40b29c

0x40b27c VSUBSD	%XMM6,%XMM1,%XMM11

0x40b280 XOR	%R9D,%R9D

0x40b283 VMULSD	%XMM5,%XMM11,%XMM12

0x40b287 VROUNDSD	$0x9,%XMM12,%XMM12,%XMM12

0x40b28d VCVTTSD2SI	%XMM12,%R8D

0x40b292 CMP	%ECX,%R8D

0x40b295 SETE	%R9B

0x40b299 SUB	%R9D,%R8D

0x40b29c VCOMISD	0x40(%RBX),%XMM0    [1]

0x40b2a1 JAE	40b388

0x40b2a7 VSUBSD	%XMM4,%XMM0,%XMM13

0x40b2ab XOR	%R9D,%R9D

0x40b2ae VMULSD	%XMM3,%XMM13,%XMM14

0x40b2b2 VROUNDSD	$0x9,%XMM14,%XMM14,%XMM14

0x40b2b8 VCVTTSD2SI	%XMM14,%EDX

0x40b2bd CMP	%ESI,%EDX

0x40b2bf SETE	%R9B

0x40b2c3 SUB	%R9D,%EDX

0x40b2c6 CMP	$-0x1,%EDX

0x40b2c9 JE	40b3c8

0x40b2cf CMP	%ECX,%R8D

0x40b2d2 JE	40b400

0x40b2d8 CMP	$-0x1,%R8D

0x40b2dc JE	40b430

0x40b2e2 CMP	%EDI,%EAX

0x40b2e4 JE	40b458

0x40b2ea CMP	$-0x1,%EAX

0x40b2ed JE	40b478

0x40b2f3 IMUL	%EDI,%R8D

0x40b2f7 ADD	%EAX,%R8D

0x40b2fa MOV	%ECX,%EAX

0x40b2fc IMUL	%EDI,%EAX

0x40b2ff IMUL	%EDX,%EAX

0x40b302 ADD	%EAX,%R8D

0x40b305 NOPL	(%RAX)

0x40b308 TEST	%R8D,%R8D

0x40b30b JS	40b486

0x40b311 CMP	0x14(%RBX),%R8D    [1]

0x40b315 JGE	40b49f

0x40b31b CMP	%R13D,%R8D

0x40b31e JE	40b368

0x40b368 MOV	-0x38(%RBP),%R15    [4]

0x40b36c INC	%R14D

0x40b36f CMP	%R14D,(%R12,%R15,1)    [2]

0x40b373 JLE	40b344

0x40b375 MOV	-0x48(%RBP),%EAX    [4]

0x40b378 LEA	(%RAX,%R14,1),%R15D

0x40b37c JMP	40b230

0x40b388 MOV	%ESI,%R11D

0x40b38b MOV	0xc(%RBX),%EDX    [1]

0x40b38e LEA	0x2(%RDI),%R9D

0x40b392 INC	%R8D

0x40b395 IMUL	%ECX,%R11D

0x40b399 IMUL	%R9D,%R8D

0x40b39d LEA	(%RDX,%R11,2),%EDX

0x40b3a1 MOV	%R9D,%R11D

0x40b3a4 IMUL	%ESI,%R11D

0x40b3a8 LEA	(%RDX,%R11,2),%EDX

0x40b3ac LEA	0x2(%RCX),%R11D

0x40b3b0 IMUL	%R9D,%R11D

0x40b3b4 ADD	%R11D,%EDX

0x40b3b7 ADD	%EDX,%R8D

0x40b3ba LEA	0x1(%R8,%RAX,1),%R8D

0x40b3bf JMP	40b308

0x40b3c8 MOV	%ESI,%R11D

0x40b3cb MOV	0xc(%RBX),%EDX    [1]

0x40b3ce LEA	0x2(%RDI),%R9D

0x40b3d2 INC	%R8D

0x40b3d5 IMUL	%ECX,%R11D

0x40b3d9 IMUL	%R9D,%R8D

0x40b3dd LEA	(%RDX,%R11,2),%EDX

0x40b3e1 MOV	%R9D,%R11D

0x40b3e4 IMUL	%ESI,%R11D

0x40b3e8 LEA	(%RDX,%R11,2),%EDX

0x40b3ec ADD	%EDX,%R8D

0x40b3ef LEA	0x1(%R8,%RAX,1),%R8D

0x40b3f4 JMP	40b308

0x40b400 MOV	%ESI,%R11D

0x40b403 MOV	0xc(%RBX),%R8D    [1]

0x40b407 LEA	0x2(%RDI),%R9D

0x40b40b IMUL	%ECX,%R11D

0x40b40f LEA	(%R8,%R11,2),%R8D

0x40b413 MOV	%R9D,%R11D

0x40b416 IMUL	%ESI,%R11D

0x40b41a IMUL	%EDX,%R9D

0x40b41e ADD	%R11D,%R8D

0x40b421 LEA	(%R8,%R9,1),%EDX

0x40b425 LEA	0x1(%RDX,%RAX,1),%R8D

0x40b42a JMP	40b308

0x40b430 MOV	%ESI,%R9D

0x40b433 MOV	0xc(%RBX),%R8D    [1]

0x40b437 IMUL	%ECX,%R9D

0x40b43b LEA	(%R8,%R9,2),%R11D

0x40b43f LEA	0x2(%RDI),%R9D

0x40b443 IMUL	%R9D,%EDX

0x40b447 ADD	%R11D,%EDX

0x40b44a LEA	0x1(%RDX,%RAX,1),%R8D

0x40b44f JMP	40b308

0x40b458 IMUL	%ECX,%EDX

0x40b45b MOV	%ESI,%R11D

0x40b45e IMUL	%ECX,%R11D

0x40b462 ADD	0xc(%RBX),%R11D    [1]

0x40b466 ADD	%R11D,%EDX

0x40b469 ADD	%EDX,%R8D

0x40b46c JMP	40b308

0x40b478 IMUL	%ECX,%EDX

0x40b47b ADD	0xc(%RBX),%EDX    [1]

0x40b47e ADD	%EDX,%R8D

0x40b481 JMP	40b308

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 373

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

Path /

Metric	Value
CQA speedup if no scalar integer	1.76
CQA speedup if FP arith vectorized	3.47
CQA speedup if fully vectorized	14.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	micro-operation queue,
Function	updateLinkCells
Source	linkCells.c:211-247,linkCells.c:295-301,linkCells.c:352-373
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.83
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	6.57
CQA cycles if fully vectorized	1.63
Front-end cycles	22.83
DIV/SQRT cycles	19.75
P0 cycles	19.75
P1 cycles	19.75
P2 cycles	19.75
P3 cycles	10.00
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	137.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.26
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.03
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Metric	Value
CQA speedup if no scalar integer	1.76
CQA speedup if FP arith vectorized	3.47
CQA speedup if fully vectorized	14.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks	micro-operation queue,
Function	updateLinkCells
Source	linkCells.c:211-247,linkCells.c:295-301,linkCells.c:352-373
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.83
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	6.57
CQA cycles if fully vectorized	1.63
Front-end cycles	22.83
DIV/SQRT cycles	19.75
P0 cycles	19.75
P1 cycles	19.75
P2 cycles	19.75
P3 cycles	10.00
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	137.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.26
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.03
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	updateLinkCells
Source file and lines	linkCells.c:211-373
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,295-301,352-373.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=28
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 28 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.83 to 13.00 cycles (1.76x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 22.83 to 1.63 cycles (14.04x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=znver4. CQA target is AMD_fam19h_mod11h (4th generation EPYC processors based on the Zen 4 microarchitecture) but specialization flags are -march=haswell
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 4 occurrences
VCOMISD: 3 occurrences
VCVTTSD2SI: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	137
loop length	496
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	22.83 cycles
front end	22.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	19.75	19.75	19.75	19.75	10.00	6.67	6.67	6.67	1.50	1.50	6.00	6.00	3.00	3.00
cycles	19.75	19.75	19.75	19.75	10.00	6.67	6.67	6.67	1.50	1.50	6.00	6.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.83
Dispatch	19.75
Overall L1	22.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.83 cycles. At this rate:

4% of peak load performance is reached (4.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.83 to 19.75 cycles (1.16x speedup).

ASM code

In the binary file, the address of the loop is: 40b230

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R15D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R8,%R8,2),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R9,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VCOMISD 0x30(%RBX),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x8(%R11),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD 0x10(%R11),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
JAE 40b272 <updateLinkCells+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM8,%XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM7,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM10,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %DL	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD 0x38(%RBX),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JAE 40b29c <updateLinkCells+0x11c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM6,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM5,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM12,%R8D	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %R9D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD 0x40(%RBX),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JAE 40b388 <updateLinkCells+0x208>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM4,%XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM3,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM14,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b3c8 <updateLinkCells+0x248>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b400 <updateLinkCells+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $-0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b430 <updateLinkCells+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b458 <updateLinkCells+0x2d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $-0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b478 <updateLinkCells+0x2f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EDI,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST %R8D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JS 40b486 <updateLinkCells+0x306>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP 0x14(%RBX),%R8D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40b49f <updateLinkCells+0x31f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %R13D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b368 <updateLinkCells+0x1e8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14D,(%R12,%R15,1)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 40b344 <updateLinkCells+0x1c4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RAX,%R14,1),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b230 <updateLinkCells+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RCX),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%R11,2),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %EDX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R8,%R9,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDX,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%R9,2),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDX,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD 0xc(%RBX),%R11D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD 0xc(%RBX),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	updateLinkCells
Source file and lines	linkCells.c:211-373
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=28
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=znver4. CQA target is AMD_fam19h_mod11h (4th generation EPYC processors based on the Zen 4 microarchitecture) but specialization flags are -march=haswell
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 4 occurrences
VCOMISD: 3 occurrences
VCVTTSD2SI: 3 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 92 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	137
loop length	496
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	22.83 cycles
front end	22.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	19.75	19.75	19.75	19.75	10.00	6.67	6.67	6.67	1.50	1.50	6.00	6.00	3.00	3.00
cycles	19.75	19.75	19.75	19.75	10.00	6.67	6.67	6.67	1.50	1.50	6.00	6.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.83
Dispatch	19.75
Overall L1	22.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.83 cycles. At this rate:

4% of peak load performance is reached (4.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40b230

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVSXD %R15D,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R8,%R8,2),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R10,%R9,8),%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%R11),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VCOMISD 0x30(%RBX),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
VMOVSD 0x8(%R11),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD 0x10(%R11),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
JAE 40b272 <updateLinkCells+0xf2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM8,%XMM2,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM7,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM10,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %DL	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %EDX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD 0x38(%RBX),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JAE 40b29c <updateLinkCells+0x11c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM6,%XMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM5,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM12,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM12,%R8D	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %R9D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCOMISD 0x40(%RBX),%XMM0	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	6	1
JAE 40b388 <updateLinkCells+0x208>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VSUBSD %XMM4,%XMM0,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VMULSD %XMM3,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VROUNDSD $0x9,%XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VCVTTSD2SI %XMM14,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	8	1
CMP %ESI,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SETE %R9B	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b3c8 <updateLinkCells+0x248>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %ECX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b400 <updateLinkCells+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $-0x1,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b430 <updateLinkCells+0x2b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %EDI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b458 <updateLinkCells+0x2d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $-0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b478 <updateLinkCells+0x2f8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EDI,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST %R8D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JS 40b486 <updateLinkCells+0x306>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP 0x14(%RBX),%R8D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40b49f <updateLinkCells+0x31f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP %R13D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40b368 <updateLinkCells+0x1e8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
INC %R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R14D,(%R12,%R15,1)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JLE 40b344 <updateLinkCells+0x1c4>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RAX,%R14,1),%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b230 <updateLinkCells+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RCX),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9D,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
INC %R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%RDX,%R11,2),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R8,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%R11,2),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
IMUL %EDX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%R8,%R9,1),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDX,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
LEA (%R8,%R9,2),%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x2(%RDI),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
IMUL %R9D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RDX,%RAX,1),%R8D	2	0	0	0.50	0.50	0	0.33	0.33	0.33	0	0	0	0	0	0	2	0.50
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD 0xc(%RBX),%R11D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
ADD %R11D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	3	1
ADD 0xc(%RBX),%EDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
ADD %EDX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 40b308 <updateLinkCells+0x188>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code