OV - exec - Loop 100

	Loop Id: 100	Module: exec	Source: timestep.c:110-116	Coverage: 0.05%

0x40f99d VMOVSD	0x8(%RDX),%XMM3    [8]

0x40f9a2 MOVSXD	(%RCX),%RSI    [7]

0x40f9a5 ADD	$0x10,%RCX

0x40f9a9 ADD	$0x60,%RDX

0x40f9ad VMOVSD	-0x60(%RDX),%XMM4    [6]

0x40f9b2 VMOVSD	-0x50(%RDX),%XMM6    [6]

0x40f9b7 VMULSD	%XMM3,%XMM3,%XMM5

0x40f9bb VMOVSD	-0x40(%RDX),%XMM8    [6]

0x40f9c0 SAL	$0x4,%RSI

0x40f9c4 VMOVSD	-0x28(%RDX),%XMM13    [6]

0x40f9c9 VDIVSD	0x8(%RDI,%RSI,1),%XMM2,%XMM7    [5]

0x40f9cf VMOVSD	-0x38(%RDX),%XMM10    [6]

0x40f9d4 VMOVSD	-0x30(%RDX),%XMM12    [6]

0x40f9d9 VMULSD	%XMM8,%XMM8,%XMM9

0x40f9de VMOVSD	-0x10(%RDX),%XMM1    [6]

0x40f9e3 MOVSXD	-0xc(%RCX),%R14    [4]

0x40f9e7 VMULSD	%XMM13,%XMM13,%XMM14

0x40f9ec VMOVSD	-0x20(%RDX),%XMM15    [6]

0x40f9f1 VMOVSD	-0x18(%RDX),%XMM3    [6]

0x40f9f6 SAL	$0x4,%R14

0x40f9fa MOVSXD	-0x8(%RCX),%RSI    [4]

0x40f9fe VFMADD231SD	%XMM4,%XMM4,%XMM5

0x40fa03 VDIVSD	0x8(%RDI,%R14,1),%XMM2,%XMM11    [2]

0x40fa0a MOVSXD	-0x4(%RCX),%R14    [4]

0x40fa0e SAL	$0x4,%RSI

0x40fa12 VDIVSD	0x8(%RDI,%RSI,1),%XMM2,%XMM4    [1]

0x40fa18 SAL	$0x4,%R14

0x40fa1c VFMADD231SD	%XMM12,%XMM12,%XMM14

0x40fa21 VFMADD132SD	%XMM6,%XMM5,%XMM6

0x40fa26 VMULSD	%XMM1,%XMM1,%XMM5

0x40fa2a VFMADD132SD	%XMM15,%XMM14,%XMM15

0x40fa2f VFMADD132SD	%XMM6,%XMM0,%XMM7

0x40fa34 VMOVSD	-0x48(%RDX),%XMM0    [6]

0x40fa39 VDIVSD	0x8(%RDI,%R14,1),%XMM2,%XMM6    [3]

0x40fa40 VFMADD231SD	%XMM3,%XMM3,%XMM5

0x40fa45 VFMADD231SD	%XMM0,%XMM0,%XMM9

0x40fa4a VMOVSD	-0x8(%RDX),%XMM0    [6]

0x40fa4f VFMADD132SD	%XMM0,%XMM5,%XMM0

0x40fa54 VFMADD132SD	%XMM10,%XMM9,%XMM10

0x40fa59 VFMADD132SD	%XMM10,%XMM7,%XMM11

0x40fa5e VFMADD132SD	%XMM15,%XMM11,%XMM4

0x40fa63 VFMADD132SD	%XMM6,%XMM4,%XMM0

0x40fa68 CMP	%RCX,%R10

0x40fa6b JNE	40f99d

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.10
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P8, P9,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	6.45
CQA cycles if fully vectorized	5.00
Front-end cycles	7.17
DIV/SQRT cycles	2.75
P0 cycles	2.75
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	0.50
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	20.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.60
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.20
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.10
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	P8, P9,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	6.45
CQA cycles if fully vectorized	5.00
Front-end cycles	7.17
DIV/SQRT cycles	2.75
P0 cycles	2.75
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	0.50
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	6.67
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	20.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	43.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.60
Nb FLOP add-sub	0.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.20
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 16.00 cycles (1.25x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	43
loop length	212
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.17 cycles
front end	7.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	0.50	6.67	6.67	6.67	10.00	10.00	0.00	0.00	0.00	0.00
cycles	2.75	2.75	2.50	2.50	0.50	6.67	6.67	6.67	10.00	10.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	7.17
Dispatch	10.00
DIV/SQRT	20.00
Data deps.	16.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

7% of peak load performance is reached (7.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f99d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
VMOVSD 0x8(%RDX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSXD (%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD -0x60(%RDX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x50(%RDX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMULSD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x40(%RDX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RDX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
VMOVSD -0x38(%RDX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x30(%RDX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x10(%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSXD -0xc(%RCX),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x20(%RDX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x18(%RDX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x8(%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD231SD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
MOVSXD -0x4(%RCX),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMOVSD -0x48(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
VFMADD231SD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD231SD %XMM0,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMOVSD -0x8(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VFMADD132SD %XMM0,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM10,%XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM15,%XMM11,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 40f99d <kineticEnergy._omp_fn.0+0x17d>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 5.00 cycles (4.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 16.00 cycles (1.25x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	43
loop length	212
used x86 registers	6
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.17 cycles
front end	7.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.50	2.50	0.50	6.67	6.67	6.67	10.00	10.00	0.00	0.00	0.00	0.00
cycles	2.75	2.75	2.50	2.50	0.50	6.67	6.67	6.67	10.00	10.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	20.00
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	7.17
Dispatch	10.00
DIV/SQRT	20.00
Data deps.	16.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

7% of peak load performance is reached (7.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40f99d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	Latency	Recip. throughput
VMOVSD 0x8(%RDX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSXD (%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
ADD $0x10,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD -0x60(%RDX),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x50(%RDX),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMULSD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x40(%RDX),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD -0x28(%RDX),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
VMOVSD -0x38(%RDX),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x30(%RDX),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x10(%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOVSXD -0xc(%RCX),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VMOVSD -0x20(%RDX),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD -0x18(%RDX),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x8(%RCX),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
VFMADD231SD %XMM4,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
MOVSXD -0x4(%RCX),%R14	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VDIVSD 0x8(%RDI,%RSI,1),%XMM2,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
SAL $0x4,%R14	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMULSD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM0,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMOVSD -0x48(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VDIVSD 0x8(%RDI,%R14,1),%XMM2,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	13	5
VFMADD231SD %XMM3,%XMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD231SD %XMM0,%XMM0,%XMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VMOVSD -0x8(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VFMADD132SD %XMM0,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM10,%XMM7,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM15,%XMM11,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
VFMADD132SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50
CMP %RCX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 40f99d <kineticEnergy._omp_fn.0+0x17d>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code