OV - exec - Loop 69

	Loop Id: 69	Module: exec	Source: haloExchange.c:633-642	Coverage: 0.03%

0x20d450 VMOVD	(%R10),%XMM1    [1]

0x20d455 VPINSRD	$0x1,0x38(%R10),%XMM1,%XMM1    [1]

0x20d45c VMOVQ	%XMM1,(%RAX,%R9,4)    [2]

0x20d462 VMOVD	0x4(%R10),%XMM1    [1]

0x20d468 VPINSRD	$0x1,0x3c(%R10),%XMM1,%XMM1    [1]

0x20d46f VMOVQ	%XMM1,(%RCX,%R9,4)    [5]

0x20d475 ADD	$0x2,%R9

0x20d479 VMOVUPD	0x8(%R10),%ZMM1    [1]

0x20d483 VMOVUPD	0x48(%R10),%YMM3    [1]

0x20d489 VMOVUPD	0x8(%R10),%YMM2    [1]

0x20d48f VMOVUPD	0x58(%R10),%XMM5    [1]

0x20d495 VMOVUPD	0x48(%R10),%XMM4    [1]

0x20d49b VBLENDPD	$0x8,0x28(%R10),%YMM2,%YMM2    [1]

0x20d4a2 VSHUFPD	$0x1,0x68(%R10),%XMM5,%XMM5    [1]

0x20d4a9 ADD	$0x70,%R10

0x20d4ad VPERMT2PD	%ZMM3,%ZMM0,%ZMM1

0x20d4b3 VMOVUPD	%XMM4,0x20(%RDX,%R11,1)    [4]

0x20d4ba VMOVUPD	%YMM2,(%RDX,%R11,1)    [4]

0x20d4c0 VMOVUPD	%XMM5,0x20(%RSI,%R11,1)    [3]

0x20d4c7 VMOVUPD	%YMM1,(%RSI,%R11,1)    [3]

0x20d4cd ADD	$0x30,%R11

0x20d4d1 CMP	%R9,%RDI

0x20d4d4 JNE	20d450

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642

--------------------------------------------------------------------------------

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	2
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	2.92
Front-end cycles	3.67
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	22.00
Nb loads	11.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	2.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	63.64
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	34.72
Vector-efficiency ratio load	31.82
Vector-efficiency ratio store	29.17
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	2
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	2.92
Front-end cycles	3.67
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	1.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	1.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	22.00
Nb loads	11.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	56.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	2.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	63.64
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	34.72
Vector-efficiency ratio load	31.82
Vector-efficiency ratio store	29.17
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	37.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

It is intermediate loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

63% of SSE/AVX loads are used in vector version.
66% of SSE/AVX stores are used in vector version.
60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 3.67 cycles (1.64x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	23
nb uops	22
loop length	138
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	3
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	5.67	5.67	5.67	1.00	2.00	2.00	1.00	3.00	3.00
cycles	1.00	1.00	0.75	0.75	0.50	6.00	6.00	6.00	1.00	2.00	2.00	1.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.67
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	66%
load	63%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	8%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	47%
load	46%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	58%

INT+FP

all	34%
load	31%
store	29%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

38% of peak load performance is reached (37.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (18.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d450

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVD (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	8	0.50
VPINSRD $0x1,0x38(%R10),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	1	0.50
VMOVQ %XMM1,(%RAX,%R9,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVD 0x4(%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	8	0.50
VPINSRD $0x1,0x3c(%R10),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	1	0.50
VMOVQ %XMM1,(%RCX,%R9,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x8(%R10),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x48(%R10),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x8(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x58(%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x48(%R10),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VBLENDPD $0x8,0x28(%R10),%YMM2,%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	1	0.50
VSHUFPD $0x1,0x68(%R10),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x70,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM3,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	0	0	0	5	1
VMOVUPD %XMM4,0x20(%RDX,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %YMM2,(%RDX,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %XMM5,0x20(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %YMM1,(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
ADD $0x30,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 20d450 <sortAtomsInCell+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

63% of SSE/AVX loads are used in vector version.
66% of SSE/AVX stores are used in vector version.
60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 3.67 cycles (1.64x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 4 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	23
nb uops	22
loop length	138
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	3
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	5.67	5.67	5.67	1.00	2.00	2.00	1.00	3.00	3.00
cycles	1.00	1.00	0.75	0.75	0.50	6.00	6.00	6.00	1.00	2.00	2.00	1.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.67
Dispatch	6.00
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	66%
load	63%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	8%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	47%
load	46%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	58%

INT+FP

all	34%
load	31%
store	29%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

38% of peak load performance is reached (37.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (18.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d450

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVD (%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	8	0.50
VPINSRD $0x1,0x38(%R10),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	1	0.50
VMOVQ %XMM1,(%RAX,%R9,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVD 0x4(%R10),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	8	0.50
VPINSRD $0x1,0x3c(%R10),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	0	1	0.50
VMOVQ %XMM1,(%RCX,%R9,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADD $0x2,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD 0x8(%R10),%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x48(%R10),%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x8(%R10),%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x58(%R10),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VMOVUPD 0x48(%R10),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VBLENDPD $0x8,0x28(%R10),%YMM2,%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	1	0.50
VSHUFPD $0x1,0x68(%R10),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x70,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM3,%ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	1	1	0	0	0	5	1
VMOVUPD %XMM4,0x20(%RDX,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %YMM2,(%RDX,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %XMM5,0x20(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVUPD %YMM1,(%RSI,%R11,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
ADD $0x30,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R9,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 20d450 <sortAtomsInCell+0x4d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

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Vector unaligned load/store instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

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Cycles summary

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

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Vectorization

Details

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code