OV - exec - Loop 67

	Loop Id: 67	Module: exec	Source: haloExchange.c:633-642	Coverage: 0.04%

0x20d500 MOV	(%RBX),%R8D    [5]

0x20d503 MOV	%R8D,(%RAX,%R15,4)    [1]

0x20d507 MOV	0x4(%RBX),%R8D    [5]

0x20d50b MOV	%R8D,(%RCX,%R15,4)    [4]

0x20d50f INC	%R15

0x20d512 VMOVSD	0x8(%RBX),%XMM0    [5]

0x20d517 VMOVSD	%XMM0,-0x10(%RDX,%RDI,1)    [2]

0x20d51d VMOVSD	0x10(%RBX),%XMM0    [5]

0x20d522 VMOVSD	%XMM0,-0x8(%RDX,%RDI,1)    [2]

0x20d528 VMOVSD	0x18(%RBX),%XMM0    [5]

0x20d52d VMOVSD	%XMM0,(%RDX,%RDI,1)    [2]

0x20d532 VMOVSD	0x20(%RBX),%XMM0    [5]

0x20d537 VMOVSD	%XMM0,-0x10(%RSI,%RDI,1)    [3]

0x20d53d VMOVSD	0x28(%RBX),%XMM0    [5]

0x20d542 VMOVSD	%XMM0,-0x8(%RSI,%RDI,1)    [3]

0x20d548 VMOVSD	0x30(%RBX),%XMM0    [5]

0x20d54d ADD	$0x38,%RBX

0x20d551 VMOVSD	%XMM0,(%RSI,%RDI,1)    [3]

0x20d556 ADD	$0x18,%RDI

0x20d55a CMP	%R12,%R15

0x20d55d JL	20d500

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642

--------------------------------------------------------------------------------

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	5.33
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	0.88
Front-end cycles	3.33
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P5, P6, P7,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	5.33
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	0.88
Front-end cycles	3.33
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	20.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	4.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	10.94
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

It is peel/tail loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.33 to 4.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 3.33 cycles (1.60x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	21
nb uops	20
loop length	95
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	1.00	1.00	0.75	0.75	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.33
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d500

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV (%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%RAX,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x4(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%RCX,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x10(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x10(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x8(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x18(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x20(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x10(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x28(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x8(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x30(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x38,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
ADD $0x18,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R12,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 20d500 <sortAtomsInCell+0x580>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.33 to 4.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 3.33 cycles (1.60x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	21
nb uops	20
loop length	95
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	1.00	1.00	0.75	0.75	0.50	5.33	5.33	5.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.33
Dispatch	5.33
Data deps.	1.00
Overall L1	5.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.50 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20d500

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV (%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%RAX,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x4(%RBX),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8D,(%RCX,%R15,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x10(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x10(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x8(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x18(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,(%RDX,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x20(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x10(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x28(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVSD %XMM0,-0x8(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD 0x30(%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x38,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD %XMM0,(%RSI,%RDI,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
ADD $0x18,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R12,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 20d500 <sortAtomsInCell+0x580>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code