OV - exec - Loop 122

	Loop Id: 122	Module: exec	Source: timestep.c:74-78	Coverage: 1.16%

0x212980 VMOVUPD	(%R12,%R14,1),%ZMM18    [2]

0x212987 VMOVUPD	0x40(%R12,%R14,1),%ZMM19    [2]

0x21298f VMOVUPD	0x40(%R15,%R14,1),%ZMM26    [3]

0x212997 VMOVUPD	0x80(%R12,%R14,1),%ZMM20    [2]

0x21299f VMOVUPD	0x80(%R15,%R14,1),%ZMM23    [3]

0x2129a7 VBROADCASTSD	(%RBX),%ZMM17    [1]

0x2129ad VMOVAPD	%ZMM18,%ZMM21

0x2129b3 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

0x2129b9 VMOVAPD	%ZMM18,%ZMM22

0x2129bf VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

0x2129c5 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

0x2129cb VMOVUPD	(%R15,%R14,1),%ZMM18    [3]

0x2129d2 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

0x2129d8 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

0x2129de VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

0x2129e4 VMOVAPD	%ZMM18,%ZMM24

0x2129ea VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

0x2129f0 VMOVAPD	%ZMM18,%ZMM25

0x2129f6 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

0x2129fc VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

0x212a02 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

0x212a08 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

0x212a0e VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

0x212a14 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

0x212a1a VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

0x212a20 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

0x212a26 VMOVAPD	%ZMM25,%ZMM17

0x212a2c VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

0x212a32 VMOVAPD	%ZMM24,%ZMM18

0x212a38 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

0x212a3e VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

0x212a44 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

0x212a4a VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

0x212a50 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

0x212a56 VMOVUPD	%ZMM24,(%R15,%R14,1)    [3]

0x212a5d VMOVUPD	%ZMM18,0x40(%R15,%R14,1)    [3]

0x212a65 VMOVUPD	%ZMM17,0x80(%R15,%R14,1)    [3]

0x212a6d ADD	$0xc0,%R14

0x212a74 ADD	$-0x8,%R8

0x212a78 JNE	212980

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.64
Bottlenecks	P9, P10,
Function	.omp_outlined..244
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	18.50
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	18.50
CQA cycles if fully vectorized	18.06
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	6.00
P8 cycles	18.50
P9 cycles	18.50
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	42.00
Nb loads	7.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.59
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.57
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	97.30
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	97.64
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	96.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.64
Bottlenecks	P9, P10,
Function	.omp_outlined..244
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	18.50
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	18.50
CQA cycles if fully vectorized	18.06
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	5.33
P5 cycles	5.33
P6 cycles	5.33
P7 cycles	6.00
P8 cycles	18.50
P9 cycles	18.50
P10 cycles	0.00
P11 cycles	3.00
P12 cycles	3.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	42.00
Nb loads	7.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.59
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.57
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	97.30
Vectorization ratio load	85.71
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	96.00
Vector-efficiency ratio all	97.64
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	96.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..244
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.50 to 18.06 cycles (1.02x speedup).

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.50 to 7.00 cycles (2.64x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	42
loop length	254
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	22
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	3.33	3.33	3.33	3.00	18.50	18.50	0.00	3.00	3.00
cycles	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	6.00	18.50	18.50	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	18.50
Data deps.	1.00
Overall L1	18.50

Vectorization ratios

all	97%
load	85%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	97%
load	87%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.50 cycles. At this rate:

22% of peak load performance is reached (21.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 212980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%R14,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%R14,1),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R15,%R14,1),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R12,%R14,1),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R15,%R14,1),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD (%R15,%R14,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM26,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM26,%ZMM7,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VFMADD231PD %ZMM21,%ZMM17,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD %ZMM22,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD %ZMM19,%ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD %ZMM25,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM24,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM25,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM24,(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM18,0x40(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM17,0x80(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
ADD $0xc0,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 212980 <.omp_outlined..244+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Function	.omp_outlined..244
Source file and lines	timestep.c:74-78
Module	exec

gain
potential
hint
expert

Vectorization

Details

97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX loads are used in vector version.
96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 3 occurrences

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 392 bytes (49 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	42
loop length	254
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	22
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	3.33	3.33	3.33	3.00	18.50	18.50	0.00	3.00	3.00
cycles	0.50	0.50	0.25	0.25	0.50	5.33	5.33	5.33	6.00	18.50	18.50	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	18.50
Data deps.	1.00
Overall L1	18.50

Vectorization ratios

all	97%
load	85%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Vector efficiency ratios

all	97%
load	87%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.50 cycles. At this rate:

22% of peak load performance is reached (21.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 212980

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%R12,%R14,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R12,%R14,1),%ZMM19	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x40(%R15,%R14,1),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R12,%R14,1),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VMOVUPD 0x80(%R15,%R14,1),%ZMM23	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VBROADCASTSD (%RBX),%ZMM17	1	0	0	0	0	0	0.33	0.33	0.33	0	0.50	0.50	0	0	5	1
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM5,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM19,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD (%R15,%R14,1),%ZMM18	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	3	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM20,%ZMM10,%ZMM19	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM26,%ZMM5,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM18,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM26,%ZMM7,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM18,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM6,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM23,%ZMM10,%ZMM26	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VFMADD231PD %ZMM21,%ZMM17,%ZMM24	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD %ZMM22,%ZMM17,%ZMM25	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD %ZMM19,%ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD %ZMM25,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM24,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVAPD %ZMM24,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM25,%ZMM13,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM25,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM14,%ZMM18	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VPERMT2PD %ZMM26,%ZMM16,%ZMM24	1	0	0	0	0	0	0	0	0	0	1	1	0	0	5	1
VMOVUPD %ZMM24,(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM18,0x40(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
VMOVUPD %ZMM17,0x80(%R15,%R14,1)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	1	1	5	2
ADD $0xc0,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD $-0x8,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 212980 <.omp_outlined..244+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code