OV - exec - Loop 107

	Loop Id: 107	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.1%

0x210420 MOV	-0x90(%RBP),%RSI

0x210427 INC	%RSI

0x21042a CMP	-0x68(%RBP),%RSI

0x21042e JE	2103b0

0x210430 MOV	-0x88(%RBP),%RAX

0x210437 MOV	(%RAX,%RSI,4),%EAX

0x21043a TEST	%EAX,%EAX

0x21043c JS	2105bc

0x210442 CMPL	$0,-0x50(%RBP)

0x210446 MOV	%RSI,-0x90(%RBP)

0x21044d JLE	210420

0x21044f MOV	-0x60(%RBP),%RSI

0x210453 MOV	(%RSI,%RAX,4),%R12D

0x210457 SAL	$0x6,%EAX

0x21045a MOVSXD	%EAX,%RDI

0x21045d LEA	(%R12,%RAX,1),%ESI

0x210461 LEA	(,%RDI,8),%RAX

0x210469 MOVSXD	%ESI,%R10

0x21046c LEA	(%RAX,%RAX,2),%RAX

0x210470 MOV	%RAX,-0xa0(%RBP)

0x210477 MOV	-0x80(%RBP),%RAX

0x21047b JMP	21048c

  (108) 0x210480 INC	%RAX

  (108) 0x210483 CMP	-0xa8(%RBP),%RAX

  (108) 0x21048a JGE	210420

  (108) 0x21048c TEST	%R12D,%R12D

  (108) 0x21048f JLE	210480

  (108) 0x210491 MOV	-0x98(%RBP),%RSI

  (108) 0x210498 MOV	-0xa0(%RBP),%R11

  (108) 0x21049f LEA	(%RAX,%RAX,2),%R13

  (108) 0x2104a3 MOV	0x20(%RSI),%R9

  (108) 0x2104a7 MOV	0x18(%R9),%R8

  (108) 0x2104ab LEA	(%R8,%R13,8),%RSI

  (108) 0x2104af LEA	0x10(%R8,%R11,1),%RBX

  (108) 0x2104b4 MOV	%RDI,%R8

  (108) 0x2104b7 JMP	2104cc

    (109) 0x2104c0 INC	%R8

    (109) 0x2104c3 ADD	$0x18,%RBX

    (109) 0x2104c7 CMP	%R10,%R8

    (109) 0x2104ca JGE	210480

    (109) 0x2104cc VMOVUPD	(%RSI),%XMM7

    (109) 0x2104d0 VSUBPD	-0x10(%RBX),%XMM7,%XMM7

    (109) 0x2104d5 VMOVAPD	%XMM7,%XMM8

    (109) 0x2104d9 VFMADD213SD	%XMM0,%XMM7,%XMM8

    (109) 0x2104de VPERMILPD	$0x1,%XMM7,%XMM9

    (109) 0x2104e4 VFMADD213SD	%XMM8,%XMM9,%XMM9

    (109) 0x2104e9 VMOVSD	0x10(%RSI),%XMM8

    (109) 0x2104ee VSUBSD	(%RBX),%XMM8,%XMM8

    (109) 0x2104f2 VFMADD231SD	%XMM8,%XMM8,%XMM9

    (109) 0x2104f7 VUCOMISD	%XMM0,%XMM9

    (109) 0x2104fb JBE	2104c0

    (109) 0x2104fd VMOVSD	(%R15),%XMM10

    (109) 0x210502 VUCOMISD	%XMM9,%XMM10

    (109) 0x210507 JB	2104c0

    (109) 0x210509 VDIVSD	%XMM9,%XMM1,%XMM9

    (109) 0x21050e MOV	0x30(%R9),%R11

    (109) 0x210512 VMOVSD	(%R11,%RAX,8),%XMM12

    (109) 0x210518 VMULSD	%XMM9,%XMM9,%XMM10

    (109) 0x21051d VMULSD	%XMM10,%XMM9,%XMM10

    (109) 0x210522 VMULSD	(%R14),%XMM10,%XMM10

    (109) 0x210527 VADDSD	%XMM2,%XMM10,%XMM11

    (109) 0x21052b VFMSUB213SD	(%RDX),%XMM10,%XMM11

    (109) 0x210530 VFMADD231SD	%XMM3,%XMM11,%XMM12

    (109) 0x210535 VMOVSD	%XMM12,(%R11,%RAX,8)

    (109) 0x21053b VFMADD213SD	-0x38(%RBP),%XMM3,%XMM11

    (109) 0x210541 VMOVSD	%XMM11,-0x38(%RBP)

    (109) 0x210546 VMULSD	(%RCX),%XMM4,%XMM11

    (109) 0x21054a MOV	0x28(%R9),%R11

    (109) 0x21054e VMULSD	%XMM11,%XMM10,%XMM11

    (109) 0x210553 VFMADD213SD	%XMM6,%XMM5,%XMM10

    (109) 0x210558 VMULSD	%XMM11,%XMM9,%XMM9

    (109) 0x21055d VMULSD	%XMM9,%XMM10,%XMM9

    (109) 0x210562 VMOVDDUP	%XMM9,%XMM10

    (109) 0x210567 VFNMADD213PD	(%R11,%R13,8),%XMM7,%XMM10

    (109) 0x21056d VMOVUPD	%XMM10,(%R11,%R13,8)

    (109) 0x210573 VFNMADD213SD	0x10(%R11,%R13,8),%XMM9,%XMM8

    (109) 0x21057a VMOVSD	%XMM8,0x10(%R11,%R13,8)

    (109) 0x210581 JMP	2104c0

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	.omp_outlined..5.120
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.63
Front-end cycles	3.67
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	2.00
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	8.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.55
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	.omp_outlined..5.120
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	0.63
Front-end cycles	3.67
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	2.00
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	8.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.55
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..5.120
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.67 to 0.62 cycles (5.87x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	22
nb uops	22
loop length	93
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	3.00	3.00	2.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	2.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	3.33
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

14% of peak load performance is reached (14.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.67 to 3.33 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 210430

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0x90(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP -0x68(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 2103b0 <.omp_outlined..5.120+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RAX,%RSI,4),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JS 2105bc <.omp_outlined..5.120+0x3ac>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMPL $0,-0x50(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JLE 210420 <.omp_outlined..5.120+0x210>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x60(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RSI,%RAX,4),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOVSXD %EAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R12,%RAX,1),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (,%RDI,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %ESI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RAX,%RAX,2),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
JMP 21048c <.omp_outlined..5.120+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	1

Function	.omp_outlined..5.120
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	22
nb uops	22
loop length	93
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	3.00	3.00	2.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	2.00	3.33	3.33	3.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	3.33
Overall L1	3.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

14% of peak load performance is reached (14.18 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.36 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 210430

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV -0x90(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP -0x68(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 2103b0 <.omp_outlined..5.120+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RAX,%RSI,4),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JS 2105bc <.omp_outlined..5.120+0x3ac>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
CMPL $0,-0x50(%RBP)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
JLE 210420 <.omp_outlined..5.120+0x210>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV -0x60(%RBP),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV (%RSI,%RAX,4),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
MOVSXD %EAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R12,%RAX,1),%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (,%RDI,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %ESI,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RAX,%RAX,2),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
JMP 21048c <.omp_outlined..5.120+0x27c>	1	0.50	0	0	0	0.50	0	0	0	0	1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code