OV - exec - Function .omp

	Function: .omp_outlined..4	Module: exec	Source: timestep.c:107-116	Coverage: 0.08%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x212500 PUSH	%RBP

0x212501 MOV	%RSP,%RBP

0x212504 PUSH	%R15

0x212506 PUSH	%R14

0x212508 PUSH	%R12

0x21250a PUSH	%RBX

0x21250b SUB	$0x20,%RSP

0x21250f MOV	(%RDX),%RAX

0x212512 MOV	0x18(%RAX),%RAX

0x212516 MOV	0xc(%RAX),%R12D

0x21251a TEST	%R12D,%R12D

0x21251d JLE	21270a

0x212523 MOV	(%RDI),%R14D

0x212526 DEC	%R12D

0x212529 MOV	%RCX,%RBX

0x21252c MOV	%RDX,%R15

0x21252f MOVL	$0,-0x28(%RBP)

0x212536 MOVL	$0x1,-0x38(%RBP)

0x21253d MOVL	$0,-0x34(%RBP)

0x212544 MOVQ	$0,-0x30(%RBP)

0x21254c MOV	%R12D,-0x24(%RBP)

0x212550 SUB	$0x8,%RSP

0x212554 LEA	-0x38(%RBP),%RAX

0x212558 LEA	-0x34(%RBP),%RCX

0x21255c LEA	-0x28(%RBP),%R8

0x212560 LEA	-0x24(%RBP),%R9

0x212564 MOV	$0x205a78,%EDI

0x212569 MOV	%R14D,%ESI

0x21256c MOV	$0x22,%EDX

0x212571 PUSH	$0x1

0x212573 PUSH	$0x1

0x212575 PUSH	%RAX

0x212576 CALL	213530 <@plt_start@+0x130>

0x21257b ADD	$0x20,%RSP

0x21257f MOV	-0x24(%RBP),%EAX

0x212582 CMP	%R12D,%EAX

0x212585 CMOVL	%EAX,%R12D

0x212589 MOVSXD	-0x28(%RBP),%RAX

0x21258d MOV	%R12D,-0x24(%RBP)

0x212591 CMP	%R12D,%EAX

0x212594 JLE	212614

0x212596 MOV	$0x205a90,%EDI

0x21259b MOV	%R14D,%ESI

0x21259e CALL	213540 <@plt_start@+0x140>

0x2125a3 LEA	-0x30(%RBP),%RAX

0x2125a7 MOV	%RAX,-0x40(%RBP)

0x2125ab SUB	$0x8,%RSP

0x2125af LEA	0x353a(%RIP),%RAX

0x2125b6 LEA	-0x40(%RBP),%R8

0x2125ba MOV	$0x205aa8,%EDI

0x2125bf MOV	$0x8,%ECX

0x2125c4 MOV	$0x212e50,%R9D

0x2125ca MOV	%R14D,%ESI

0x2125cd MOV	$0x1,%EDX

0x2125d2 PUSH	%RAX

0x2125d3 CALL	213570 <@plt_start@+0x170>

0x2125d8 ADD	$0x10,%RSP

0x2125dc CMP	$0x2,%EAX

0x2125df JE	2126d9

0x2125e5 CMP	$0x1,%EAX

0x2125e8 JNE	21270a

0x2125ee VMOVSD	(%RBX),%XMM0

0x2125f2 LEA	0x34f7(%RIP),%RDX

0x2125f9 MOV	$0x205aa8,%EDI

0x2125fe MOV	%R14D,%ESI

0x212601 VADDSD	-0x30(%RBP),%XMM0,%XMM0

0x212606 VMOVSD	%XMM0,(%RBX)

0x21260a CALL	213580 <@plt_start@+0x180>

0x21260f JMP	21270a

0x212614 MOV	(%R15),%RCX

0x212617 VMOVSD	-0x10627(%RIP),%XMM1

0x21261f MOV	%EAX,%ESI

0x212621 SAL	$0x6,%ESI

0x212624 MOVSXD	%R12D,%RDI

0x212627 VXORPD	%XMM0,%XMM0,%XMM0

0x21262b MOV	0x18(%RCX),%RDX

0x21262f MOV	0x78(%RDX),%RDX

0x212633 JMP	212653

0x212635 NOPW	%CS:(%RAX,%RAX,1)

(118) 0x212640 ADD	$0x40,%ESI

(118) 0x212643 LEA	0x1(%RAX),%R8

(118) 0x212647 CMP	%RDI,%RAX

(118) 0x21264a MOV	%R8,%RAX

(118) 0x21264d JGE	212596

(118) 0x212653 MOV	(%RDX,%RAX,4),%R8D

(118) 0x212657 TEST	%R8D,%R8D

(118) 0x21265a JLE	212640

(118) 0x21265c MOV	0x20(%RCX),%R15

(118) 0x212660 MOVSXD	%ESI,%R9

(118) 0x212663 LEA	(,%R9,8),%R10

(118) 0x21266b SAL	$0x2,%R9

(118) 0x21266f LEA	(%R10,%R10,2),%R11

(118) 0x212673 MOV	0x28(%RCX),%R10

(118) 0x212677 MOV	0x20(%R15),%R12

(118) 0x21267b ADD	0x10(%R15),%R9

(118) 0x21267f XOR	%R15D,%R15D

(118) 0x212682 LEA	0x10(%R12,%R11,1),%R11

(118) 0x212687 NOPW	(%RAX,%RAX,1)

  (119) 0x212690 MOVSXD	(%R9,%R15,4),%R12

  (119) 0x212694 VMOVSD	-0x8(%R11),%XMM4

  (119) 0x21269a VMOVSD	-0x10(%R11),%XMM3

  (119) 0x2126a0 INC	%R15

  (119) 0x2126a3 SAL	$0x4,%R12

  (119) 0x2126a7 VDIVSD	0x8(%R10,%R12,1),%XMM1,%XMM2

  (119) 0x2126ae VMULSD	%XMM4,%XMM4,%XMM4

  (119) 0x2126b2 VFMADD231SD	%XMM3,%XMM3,%XMM4

  (119) 0x2126b7 VMOVSD	(%R11),%XMM3

  (119) 0x2126bc ADD	$0x18,%R11

  (119) 0x2126c0 VFMADD213SD	%XMM4,%XMM3,%XMM3

  (119) 0x2126c5 VFMADD231SD	%XMM3,%XMM2,%XMM0

  (119) 0x2126ca VMOVSD	%XMM0,-0x30(%RBP)

  (119) 0x2126cf CMP	%R15D,%R8D

  (119) 0x2126d2 JNE	212690

(118) 0x2126d4 JMP	212640

0x2126d9 VMOVSD	-0x30(%RBP),%XMM0

0x2126de VMOVSD	(%RBX),%XMM1

0x2126e2 NOPW	%CS:(%RAX,%RAX,1)

(117) 0x2126f0 VADDSD	%XMM0,%XMM1,%XMM2

(117) 0x2126f4 VMOVQ	%XMM1,%RAX

(117) 0x2126f9 VMOVQ	%XMM2,%RCX

(117) 0x2126fe LOCK CMPXCHG	%RCX,(%RBX)

(117) 0x212703 VMOVQ	%RAX,%XMM1

(117) 0x212708 JNE	2126f0

0x21270a ADD	$0x20,%RSP

0x21270e POP	%RBX

0x21270f POP	%R12

0x212711 POP	%R14

0x212713 POP	%R15

0x212715 POP	%RBP

0x212716 RET

0x212717 INT	$0x3

0x212718 INT	$0x3

0x212719 INT	$0x3

0x21271a INT	$0x3

0x21271b INT	$0x3

0x21271c INT	$0x3

0x21271d INT	$0x3

0x21271e INT	$0x3

0x21271f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 3.17 cycles (4.79x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 15.17 to 1.33 cycles (11.38x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 96 bytes (12 double precision FP elements). The binary function is storing 44 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	91
loop length	365
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.25	9.25	5.50	8.67	8.67	8.67	0.00	0.00	0.50	0.50	0.50	0.50
cycles	9.50	9.50	9.25	9.25	5.50	8.67	8.67	8.67	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	9.50
Overall L1	15.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	14%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	6%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

6% of peak load performance is reached (6.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.17 to 9.50 cycles (1.60x speedup).

ASM code

In the binary file, the address of the function is: 212500

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xc(%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205a78,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213530 <@plt_start@+0x130>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x24(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 212614 <.omp_outlined..4+0x114>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x205a90,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 213540 <@plt_start@+0x140>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x353a(%RIP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205aa8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x8,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212e50,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213570 <@plt_start@+0x170>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2126d9 <.omp_outlined..4+0x1d9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x34f7(%RIP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205aa8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD -0x30(%RBP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CALL 213580 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV (%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD -0x10627(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %R12D,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x18(%RCX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JMP 212653 <.omp_outlined..4+0x153>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 3.17 cycles (4.79x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 96 bytes (12 double precision FP elements). The binary function is storing 44 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	91
loop length	365
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	9.50	9.50	9.25	9.25	5.50	8.67	8.67	8.67	0.00	0.00	0.50	0.50	0.50	0.50
cycles	9.50	9.50	9.25	9.25	5.50	8.67	8.67	8.67	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	9.50
Overall L1	15.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	14%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	6%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

6% of peak load performance is reached (6.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.90 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 212500

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0xc(%RAX),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R12D,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%RDI),%R14D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
DEC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVQ $0,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x38(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x28(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205a78,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213530 <@plt_start@+0x130>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x24(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %EAX,%R12D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %R12D,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R12D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 212614 <.omp_outlined..4+0x114>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x205a90,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 213540 <@plt_start@+0x140>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
LEA -0x30(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x353a(%RIP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x40(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205aa8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x8,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x212e50,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213570 <@plt_start@+0x170>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 2126d9 <.omp_outlined..4+0x1d9>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD (%RBX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA 0x34f7(%RIP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205aa8,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD -0x30(%RBP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
CALL 213580 <@plt_start@+0x180>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 21270a <.omp_outlined..4+0x20a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV (%R15),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD -0x10627(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%ESI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVSXD %R12D,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x18(%RCX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JMP 212653 <.omp_outlined..4+0x153>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
▼.omp_outlined..4–	0.08	0.01
○Loop 117 - timestep.c:107-107 - exec	0	0
▼Loop 118 - timestep.c:108-116 - exec–	0	0
○Loop 119 - timestep.c:110-116 - exec	0.08	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code