OV - exec - Function .omp

	Function: .omp_outlined..119	Module: exec	Source: ljForce.c:157-161 [...]	Coverage: 2.08%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 23 - 23

--------------------------------------------------------------------------------

23:    a[1] = 0.0;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 161

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

0x210120 PUSH	%RBP

0x210121 MOV	%RSP,%RBP

0x210124 PUSH	%R15

0x210126 PUSH	%R14

0x210128 PUSH	%RBX

0x210129 SUB	$0x18,%RSP

0x21012d MOV	(%RDX),%R15D

0x210130 TEST	%R15D,%R15D

0x210133 JLE	2101fd

0x210139 MOV	(%RDI),%EBX

0x21013b DEC	%R15D

0x21013e MOV	%RCX,%R14

0x210141 MOVL	$0,-0x20(%RBP)

0x210148 MOVL	$0x1,-0x28(%RBP)

0x21014f MOVL	$0,-0x24(%RBP)

0x210156 MOV	%R15D,-0x1c(%RBP)

0x21015a SUB	$0x8,%RSP

0x21015e MOV	%EBX,%ESI

0x210160 LEA	-0x28(%RBP),%RAX

0x210164 LEA	-0x24(%RBP),%RCX

0x210168 LEA	-0x20(%RBP),%R8

0x21016c LEA	-0x1c(%RBP),%R9

0x210170 MOV	$0x205940,%EDI

0x210175 MOV	$0x22,%EDX

0x21017a PUSH	$0x1

0x21017c PUSH	$0x1

0x21017e PUSH	%RAX

0x21017f CALL	213530 <@plt_start@+0x130>

0x210184 ADD	$0x20,%RSP

0x210188 MOV	-0x1c(%RBP),%EAX

0x21018b MOVSXD	-0x20(%RBP),%RSI

0x21018f CMP	%R15D,%EAX

0x210192 CMOVL	%EAX,%R15D

0x210196 MOV	%R15D,-0x1c(%RBP)

0x21019a CMP	%R15D,%ESI

0x21019d JG	2101f1

0x21019f MOV	(%R14),%RAX

0x2101a2 LEA	-0x1(%RSI),%RDX

0x2101a6 LEA	(%RSI,%RSI,2),%RSI

0x2101aa MOVSXD	%R15D,%RCX

0x2101ad VXORPS	%XMM0,%XMM0,%XMM0

0x2101b1 SAL	$0x3,%RSI

0x2101b5 MOV	0x20(%RAX),%RDI

0x2101b9 MOV	0x30(%RDI),%RAX

0x2101bd ADD	0x28(%RDI),%RSI

0x2101c1 NOPW	%CS:(%RAX,%RAX,1)

(104) 0x2101d0 VMOVUPS	%XMM0,(%RSI)

(104) 0x2101d4 MOVQ	$0,0x10(%RSI)

(104) 0x2101dc MOVQ	$0,0x8(%RAX,%RDX,8)

(104) 0x2101e5 INC	%RDX

(104) 0x2101e8 ADD	$0x18,%RSI

(104) 0x2101ec CMP	%RCX,%RDX

(104) 0x2101ef JL	2101d0

0x2101f1 MOV	$0x205958,%EDI

0x2101f6 MOV	%EBX,%ESI

0x2101f8 CALL	213540 <@plt_start@+0x140>

0x2101fd ADD	$0x18,%RSP

0x210201 POP	%RBX

0x210202 POP	%R14

0x210204 POP	%R15

0x210206 POP	%RBP

0x210207 RET

0x210208 INT	$0x3

0x210209 INT	$0x3

0x21020a INT	$0x3

0x21020b INT	$0x3

0x21020c INT	$0x3

0x21020d INT	$0x3

0x21020e INT	$0x3

0x21020f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.75 cycles (5.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.33 to 0.69 cycles (13.58x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	63
nb uops	56
loop length	207
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.00	6.00	2.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.25	6.25	6.00	6.00	2.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.33
Dispatch	6.25
Overall L1	9.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.33 to 6.25 cycles (1.49x speedup).

ASM code

In the binary file, the address of the function is: 210120

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 2101fd <.omp_outlined..119+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
DEC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R15D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205940,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213530 <@plt_start@+0x130>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x1c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD -0x20(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMP %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %EAX,%R15D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R15D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R15D,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JG 2101f1 <.omp_outlined..119+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x1(%RSI),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RSI,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R15D,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x20(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD 0x28(%RDI),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x205958,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 213540 <@plt_start@+0x140>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.75 cycles (5.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	63
nb uops	56
loop length	207
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.25	6.25	6.00	6.00	2.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.25	6.25	6.00	6.00	2.50	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.33
Dispatch	6.25
Overall L1	9.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

5% of peak load performance is reached (5.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (2.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 210120

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV (%RDX),%R15D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 2101fd <.omp_outlined..119+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
DEC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x28(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0,-0x24(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R15D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x28(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x24(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x205940,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 213530 <@plt_start@+0x130>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x1c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSXD -0x20(%RBP),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
CMP %R15D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMOVL %EAX,%R15D	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R15D,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %R15D,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JG 2101f1 <.omp_outlined..119+0xd1>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x1(%RSI),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RSI,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R15D,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x20(%RAX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
ADD 0x28(%RDI),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x205958,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 213540 <@plt_start@+0x140>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
▼.omp_outlined..119–	2.08	0.24
○Loop 104 - ljForce.c:158-161 - exec	2.08	0.23

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