OV - exec - Loop 152

	Loop Id: 152	Module: exec	Source: timestep.c:110-115	Coverage: 0.01%

0x40dcb0 LDR	W11, [X15, X8,LSL #2]

0x40dcb4 UBFM	W9, W8, #26, #25

0x40dcb8 CMP	W11, #0

0x40dcbc B.LE	40e00c

0x40dcc0 LDP	X2, X12, [X19, #32]

0x40dcc4 SUB	W3, W11, #1

0x40dcc8 LDR	X18, [X2, #16]

0x40dccc LDR	X10, [X2, #32]

0x40dcd0 CMP	W3, #6

0x40dcd4 B.LS	40e050

0x40dcd8 ADD	X13, X8, X8,LSL #1

0x40dcdc UBFM	X7, X8, #56, #55

0x40dce0 UBFM	W4, W11, #2, #31

0x40dce4 MOVI	V0.2D, #0

0x40dce8 ADD	X5, X18, X7

0x40dcec ADD	X30, X12, #8

0x40dcf0 ADD	X21, X5, W4,UXTW #4

0x40dcf4 ADD	X14, X10, X13,LSL #9

0x40dcf8 ORR	X22, XZR, X5

0x40dcfc TBZ	W4, #0, 40dd80

0x40dd00 LD3	{V25.2D, V26.2D, V27.2D}, [X14]

0x40dd04 ADD	X23, X14, #48

0x40dd08 ADD	X22, X5, #16

0x40dd0c ORR	V0.16B, V5.16B, V5.16B

0x40dd10 ADD	X14, X14, #96

0x40dd14 LD3	{V28.2D, V29.2D, V30.2D}, [X23]

0x40dd18 LDR	W0, [X18, X7]

0x40dd1c ADD	X1, X30, W0,SXTW #4

0x40dd20 LDR	D22, [X1]

0x40dd24 LDP	W3, W2, [X5, #4]

0x40dd28 ADD	X6, X30, W2,SXTW #4

0x40dd2c ADD	X7, X30, W3,SXTW #4

0x40dd30 FMUL	V23.2D, V26.2D, V26.2D

0x40dd34 LDR	D24, [X6]

0x40dd38 LD1	{V22.D[1]}, [X7]

0x40dd3c FMUL	V31.2D, V29.2D, V29.2D

0x40dd40 LDR	W13, [X5, #12]

0x40dd44 ADD	X4, X30, W13,SXTW #4

0x40dd48 FMLA	V23.2D, V25.2D, V25.2D

0x40dd4c LD1	{V24.D[1]}, [X4]

0x40dd50 FMLA	V31.2D, V28.2D, V28.2D

0x40dd54 FMLA	V23.2D, V27.2D, V27.2D

0x40dd58 FDIV	V1.2D, V16.2D, V22.2D

0x40dd5c FMLA	V31.2D, V30.2D, V30.2D

0x40dd60 FDIV	V2.2D, V16.2D, V24.2D

0x40dd64 FMLA	V0.2D, V1.2D, V23.2D

0x40dd68 FMLA	V0.2D, V2.2D, V31.2D

0x40dd6c CMP	X21, X22

0x40dd70 B.EQ	40de54

0x40dd74 HINT	#0

0x40dd78 HINT	#0

0x40dd7c HINT	#0

  (154) 0x40dd80 ADD	X23, X14, #48

  (154) 0x40dd84 LDP	W1, W2, [X22]

  (154) 0x40dd88 ADD	X7, X30, W1,SXTW #4

  (154) 0x40dd8c ADD	X0, X14, #96

  (154) 0x40dd90 ADD	X6, X30, W2,SXTW #4

  (154) 0x40dd94 ADD	X5, X14, #144

  (154) 0x40dd98 ADD	X3, X22, #16

  (154) 0x40dd9c LD3	{V25.2D, V26.2D, V27.2D}, [X14]

  (154) 0x40dda0 ADD	X14, X14, #192

  (154) 0x40dda4 LD3	{V28.2D, V29.2D, V30.2D}, [X23]

  (154) 0x40dda8 LD3	{V19.2D, V20.2D, V21.2D}, [X0]

  (154) 0x40ddac LD3	{V22.2D, V23.2D, V24.2D}, [X5]

  (154) 0x40ddb0 LDR	D4, [X7]

  (154) 0x40ddb4 FMUL	V3.2D, V26.2D, V26.2D

  (154) 0x40ddb8 LDP	W13, W4, [X22, #8]

  (154) 0x40ddbc ADD	X23, X30, W13,SXTW #4

  (154) 0x40ddc0 ADD	X1, X30, W4,SXTW #4

  (154) 0x40ddc4 FMUL	V26.2D, V29.2D, V29.2D

  (154) 0x40ddc8 LDR	W22, [X22, #16]

  (154) 0x40ddcc ADD	X0, X30, W22,SXTW #4

  (154) 0x40ddd0 LD1	{V4.D[1]}, [X6]

  (154) 0x40ddd4 FMLA	V3.2D, V25.2D, V25.2D

  (154) 0x40ddd8 ADD	X22, X3, #16

  (154) 0x40dddc LDR	D25, [X23]

  (154) 0x40dde0 FMUL	V18.2D, V20.2D, V20.2D

  (154) 0x40dde4 LDP	W5, W2, [X3, #4]

  (154) 0x40dde8 ADD	X7, X30, W2,SXTW #4

  (154) 0x40ddec ADD	X6, X30, W5,SXTW #4

  (154) 0x40ddf0 FMLA	V26.2D, V28.2D, V28.2D

  (154) 0x40ddf4 LDR	D29, [X7]

  (154) 0x40ddf8 FMLA	V3.2D, V27.2D, V27.2D

  (154) 0x40ddfc LDR	D27, [X0]

  (154) 0x40de00 FDIV	V17.2D, V16.2D, V4.2D

  (154) 0x40de04 LD1	{V25.D[1]}, [X1]

  (154) 0x40de08 FMLA	V26.2D, V30.2D, V30.2D

  (154) 0x40de0c LDR	W3, [X3, #12]

  (154) 0x40de10 ADD	X13, X30, W3,SXTW #4

  (154) 0x40de14 LD1	{V27.D[1]}, [X6]

  (154) 0x40de18 FMLA	V18.2D, V19.2D, V19.2D

  (154) 0x40de1c LD1	{V29.D[1]}, [X13]

  (154) 0x40de20 FMLA	V0.2D, V17.2D, V3.2D

  (154) 0x40de24 FDIV	V20.2D, V16.2D, V25.2D

  (154) 0x40de28 FMUL	V30.2D, V23.2D, V23.2D

  (154) 0x40de2c FMLA	V18.2D, V21.2D, V21.2D

  (154) 0x40de30 FDIV	V19.2D, V16.2D, V27.2D

  (154) 0x40de34 FMLA	V0.2D, V20.2D, V26.2D

  (154) 0x40de38 FDIV	V21.2D, V16.2D, V29.2D

  (154) 0x40de3c FMLA	V30.2D, V22.2D, V22.2D

  (154) 0x40de40 FMLA	V0.2D, V19.2D, V18.2D

  (154) 0x40de44 FMLA	V30.2D, V24.2D, V24.2D

  (154) 0x40de48 FMLA	V0.2D, V21.2D, V30.2D

  (154) 0x40de4c CMP	X21, X22

  (154) 0x40de50 B.NE	40dd80

0x40de54 FADDP	D28, V0.2D

0x40de58 FADD	D7, D7, D28

0x40de5c ANDS	XZR, X11, #4160

0x40de60 B.EQ	40e00c

0x40e00c ADD	X8, X8, #1

0x40e010 CMP	W17, W8

0x40e014 B.GT	40dcb0

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 115

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.56 - 2.00
Bottlenecks	P8, P10,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-115
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00 - 13.99
CQA cycles if no scalar integer	6.99 - 13.99
CQA cycles if FP arith vectorized	6.99 - 13.99
CQA cycles if fully vectorized	6.99 - 13.99
Front-end cycles	7.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.83
P3 cycles	3.83
P4 cycles	3.83
P5 cycles	3.83
P6 cycles	3.83
P7 cycles	3.83
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	4.33
P13 cycles	4.33
P14 cycles	4.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.86 - 2.43
Nb FLOP add-sub	2.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.87 - 25.71
Bytes prefetched	0.00
Bytes loaded	180.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.14
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	12.50
Vector-efficiency ratio all	65.00
Vector-efficiency ratio load	52.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.57
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	46.88

Metric	Value
CQA speedup if no scalar integer	1.00 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.56 - 2.00
Bottlenecks	P8, P10,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-115
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00 - 13.99
CQA cycles if no scalar integer	6.99 - 13.99
CQA cycles if FP arith vectorized	6.99 - 13.99
CQA cycles if fully vectorized	6.99 - 13.99
Front-end cycles	7.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.83
P3 cycles	3.83
P4 cycles	3.83
P5 cycles	3.83
P6 cycles	3.83
P7 cycles	3.83
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	4.33
P13 cycles	4.33
P14 cycles	4.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.86 - 2.43
Nb FLOP add-sub	2.00
Nb FLOP mul	4.00
Nb FLOP fma	12.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.87 - 25.71
Bytes prefetched	0.00
Bytes loaded	180.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	37.14
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	12.50
Vector-efficiency ratio all	65.00
Vector-efficiency ratio load	52.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.57
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	46.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-115
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-115.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 65% of vector register length is used (average across all VPU instructions).

Details

37% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction (12 inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 180 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.83	3.83	3.83	3.83	3.83	3.83	4.50	4.50	4.50	4.50	4.33	4.33	4.33	0.00	0.00
cycles	3.00	3.00	3.83	3.83	3.83	3.83	3.83	3.83	4.50	4.50	4.50	4.50	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

6.99-13.99

Cycles summary

Front-end	7.00
Overall L1	7.00-13.99

Vectorization ratios

INT

all	13%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	0%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	0%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles. At this rate:

13% of peak load performance is reached (12.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40e00c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W11, [X15, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM W9, W8, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40e00c <kineticEnergy._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X12, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W3, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X18, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W3, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 40e050 <kineticEnergy._omp_fn.0+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X8, X8,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X8, #56, #55	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W4, W11, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X5, X18, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X5, W4,UXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X14, X10, X13,LSL #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W4, #0, 40dd80 <kineticEnergy._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD3 {V25.2D, V26.2D, V27.2D}, [X14]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	1	vect (100.0%)
ADD X23, X14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X5, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR V0.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X14, X14, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD3 {V28.2D, V29.2D, V30.2D}, [X23]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	1	vect (100.0%)
LDR W0, [X18, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X30, W0,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR D22, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP W3, W2, [X5, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X30, W2,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X7, X30, W3,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMUL V23.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR D24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LD1 {V22.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FMUL V31.2D, V29.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR W13, [X5, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X30, W13,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMLA V23.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
LD1 {V24.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FMLA V31.2D, V28.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V27.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FDIV V1.2D, V16.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V31.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FDIV V2.2D, V16.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V0.2D, V1.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
CMP X21, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de54 <kineticEnergy._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FADDP D28, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD D7, D7, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40e00c <kineticEnergy._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W17, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40dcb0 <kineticEnergy._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-115
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-115.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 65% of vector register length is used (average across all VPU instructions).

Details

37% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 34 FP arithmetical operations:

14: addition or subtraction (12 inside FMA instructions)
16: multiply (12 inside FMA instructions)
4: divide

The binary loop is loading 180 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.83	3.83	3.83	3.83	3.83	3.83	4.50	4.50	4.50	4.50	4.33	4.33	4.33	0.00	0.00
cycles	3.00	3.00	3.83	3.83	3.83	3.83	3.83	3.83	4.50	4.50	4.50	4.50	4.33	4.33	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

6.99-13.99

Cycles summary

Front-end	7.00
Overall L1	7.00-13.99

Vectorization ratios

INT

all	13%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	0%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	37%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	0%
fma	100%
div/sqrt	100%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.99 cycles. At this rate:

13% of peak load performance is reached (12.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40e00c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W11, [X15, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM W9, W8, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40e00c <kineticEnergy._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X12, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB W3, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X18, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W3, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 40e050 <kineticEnergy._omp_fn.0+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X8, X8,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X8, #56, #55	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W4, W11, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X5, X18, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X21, X5, W4,UXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X14, X10, X13,LSL #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ORR X22, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W4, #0, 40dd80 <kineticEnergy._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD3 {V25.2D, V26.2D, V27.2D}, [X14]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	1	vect (100.0%)
ADD X23, X14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X5, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR V0.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD X14, X14, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LD3 {V28.2D, V29.2D, V30.2D}, [X23]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	1	vect (100.0%)
LDR W0, [X18, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X30, W0,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR D22, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP W3, W2, [X5, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X30, W2,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X7, X30, W3,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMUL V23.2D, V26.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR D24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LD1 {V22.D[1]}, [X7]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FMUL V31.2D, V29.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (100.0%)
LDR W13, [X5, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X30, W13,SXTW #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMLA V23.2D, V25.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
LD1 {V24.D[1]}, [X4]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33	scal (50.0%)
FMLA V31.2D, V28.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V27.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FDIV V1.2D, V16.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V31.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FDIV V2.2D, V16.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FMLA V0.2D, V1.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	vect (100.0%)
CMP X21, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de54 <kineticEnergy._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FADDP D28, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FADD D7, D7, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ANDS XZR, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40e00c <kineticEnergy._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W17, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40dcb0 <kineticEnergy._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code