OV - exec - Loop 147

	Loop Id: 147	Module: exec	Source: timestep.c:74-78	Coverage: 0.58%

0x40d850 LDR	W20, [X12, X10,LSL #2]

0x40d854 CMP	W20, #0

0x40d858 B.LE	40da58

0x40d85c LDR	X5, [X13, #32]

0x40d860 LDP	X16, X8, [X5, #32]

0x40d864 ADD	X18, X16, X3

0x40d868 ADD	X6, X8, X3

0x40d86c CMP	W20, #1

0x40d870 B.EQ	40da78

0x40d874 ADD	X7, X3, #48

0x40d878 ADD	X6, X8, X3

0x40d87c ADD	X9, X16, X7

0x40d880 ADD	X17, X8, X7

0x40d884 CMP	X6, X9

0x40d888 ADD	X18, X16, X3

0x40d88c CCMP	X18, X17, #2, #3

0x40d890 B.CC	40da78

0x40d894 UBFM	W21, W20, #1, #31

0x40d898 ORR	X19, XZR, #3841

0x40d89c MOVK	X19, #43691

0x40d8a0 ORR	X0, XZR, X18

0x40d8a4 UMADDL	X11, W21, W14, X18

0x40d8a8 MOVK	X19, #2730

0x40d8ac ORR	X1, XZR, X6

0x40d8b0 SUB	X2, X11, X18

0x40d8b4 SUB	X4, X2, #48

0x40d8b8 UBFM	X5, X4, #4, #63

0x40d8bc MADD	X7, X5, X19, XZR

0x40d8c0 ADD	X9, X7, #1

0x40d8c4 ANDS	X17, X9, #4160

0x40d8c8 B.EQ	40d960

0x40d8cc CMP	X17, #1

0x40d8d0 B.EQ	40d930

0x40d8d4 CMP	X17, #2

0x40d8d8 B.EQ	40d908

0x40d8dc LDP	Q1, Q0, [X18, #16]

0x40d8e0 ADD	X0, X18, #48

0x40d8e4 ADD	X1, X6, #48

0x40d8e8 LDP	Q3, Q2, [X6, #16]

0x40d8ec LDR	Q21, [X8, X3]

0x40d8f0 LDR	Q20, [X16, X3]

0x40d8f4 FMLA	V1.2D, V30.2D, V3.2D

0x40d8f8 FMLA	V20.2D, V30.2D, V21.2D

0x40d8fc FMLA	V0.2D, V30.2D, V2.2D

0x40d900 STR	Q20, [X16, X3]

0x40d904 STP	Q1, Q0, [X18, #16]

0x40d908 LDR	Q22, [X1, #32]

0x40d90c LDP	Q6, Q19, [X0]

0x40d910 ADD	X0, X0, #48

0x40d914 LDP	Q7, Q23, [X1], #48

0x40d918 LDUR	Q18, [X0, #496]

0x40d91c FMLA	V18.2D, V30.2D, V22.2D

0x40d920 FMLA	V19.2D, V30.2D, V23.2D

0x40d924 FMLA	V6.2D, V30.2D, V7.2D

0x40d928 STUR	Q18, [X0, #496]

0x40d92c STP	Q6, Q19, [X0, #2000]

0x40d930 LDR	Q16, [X1, #32]

0x40d934 LDP	Q4, Q25, [X0]

0x40d938 ADD	X0, X0, #48

0x40d93c LDP	Q5, Q17, [X1], #48

0x40d940 LDUR	Q24, [X0, #496]

0x40d944 FMLA	V24.2D, V30.2D, V16.2D

0x40d948 FMLA	V25.2D, V30.2D, V17.2D

0x40d94c FMLA	V4.2D, V30.2D, V5.2D

0x40d950 STUR	Q24, [X0, #496]

0x40d954 STP	Q4, Q25, [X0, #2000]

0x40d958 CMP	X0, X11

0x40d95c B.EQ	40da14

  (149) 0x40d960 LDP	Q27, Q26, [X1, #16]

  (149) 0x40d964 ORR	X21, XZR, X1

  (149) 0x40d968 ADD	X19, X0, #48

  (149) 0x40d96c ADD	X6, X0, #96

  (149) 0x40d970 ADD	X18, X1, #96

  (149) 0x40d974 LDP	Q28, Q3, [X0, #32]

  (149) 0x40d978 ADD	X2, X0, #144

  (149) 0x40d97c ADD	X4, X1, #144

  (149) 0x40d980 ADD	X1, X1, #192

  (149) 0x40d984 LDP	Q21, Q29, [X0]

  (149) 0x40d988 ADD	X0, X0, #192

  (149) 0x40d98c LDR	Q20, [X21], #48

  (149) 0x40d990 FMLA	V28.2D, V30.2D, V26.2D

  (149) 0x40d994 FMLA	V29.2D, V30.2D, V27.2D

  (149) 0x40d998 FMLA	V21.2D, V30.2D, V20.2D

  (149) 0x40d99c STUR	Q28, [X0, #352]

  (149) 0x40d9a0 STP	Q21, Q29, [X0, #1856]

  (149) 0x40d9a4 LDP	Q2, Q6, [X19, #16]

  (149) 0x40d9a8 LDP	Q1, Q0, [X21, #16]

  (149) 0x40d9ac LDUR	Q19, [X1, #368]

  (149) 0x40d9b0 FMLA	V3.2D, V30.2D, V19.2D

  (149) 0x40d9b4 FMLA	V2.2D, V30.2D, V1.2D

  (149) 0x40d9b8 FMLA	V6.2D, V30.2D, V0.2D

  (149) 0x40d9bc STUR	Q3, [X0, #368]

  (149) 0x40d9c0 STP	Q2, Q6, [X19, #16]

  (149) 0x40d9c4 LDP	Q22, Q7, [X6, #16]

  (149) 0x40d9c8 LDP	Q23, Q18, [X18, #16]

  (149) 0x40d9cc LDUR	Q25, [X1, #416]

  (149) 0x40d9d0 LDUR	Q4, [X0, #416]

  (149) 0x40d9d4 FMLA	V22.2D, V30.2D, V23.2D

  (149) 0x40d9d8 FMLA	V4.2D, V30.2D, V25.2D

  (149) 0x40d9dc FMLA	V7.2D, V30.2D, V18.2D

  (149) 0x40d9e0 STUR	Q4, [X0, #416]

  (149) 0x40d9e4 STP	Q22, Q7, [X6, #16]

  (149) 0x40d9e8 LDP	Q16, Q5, [X2, #16]

  (149) 0x40d9ec LDP	Q24, Q17, [X4, #16]

  (149) 0x40d9f0 LDUR	Q21, [X0, #464]

  (149) 0x40d9f4 LDUR	Q29, [X1, #464]

  (149) 0x40d9f8 FMLA	V16.2D, V30.2D, V24.2D

  (149) 0x40d9fc FMLA	V21.2D, V30.2D, V29.2D

  (149) 0x40da00 FMLA	V5.2D, V30.2D, V17.2D

  (149) 0x40da04 STUR	Q21, [X0, #464]

  (149) 0x40da08 STP	Q16, Q5, [X2, #16]

  (149) 0x40da0c CMP	X0, X11

  (149) 0x40da10 B.NE	40d960

0x40da14 AND	W11, W20, #1951

0x40da18 TBZ	W20, #0, 40da58

0x40da1c ADD	W20, W11, W10,LSL #6

0x40da20 SMADDL	X5, W20, W15, XZR

0x40da24 LDR	D27, [X8, X5]

0x40da28 ADD	X7, X16, X5

0x40da2c ADD	X8, X8, X5

0x40da30 LDR	D26, [X16, X5]

0x40da34 FMADD	D20, D31, D27, D26

0x40da38 STR	D20, [X16, X5]

0x40da3c LDR	D2, [X8, #8]

0x40da40 LDP	D3, D28, [X7, #8]

0x40da44 FMADD	D6, D31, D2, D3

0x40da48 STR	D6, [X7, #8]

0x40da4c LDR	D1, [X8, #16]

0x40da50 FMADD	D0, D31, D1, D28

0x40da54 STR	D0, [X7, #16]

0x40da58 ADD	X10, X10, #1

0x40da5c ADD	X3, X3, #1536

0x40da60 CMP	W30, W10

0x40da64 B.GT	40d850

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
►98.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.26
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.13
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	10.94
CQA cycles if fully vectorized	9.13
Front-end cycles	11.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	6.92
P3 cycles	6.92
P4 cycles	6.83
P5 cycles	6.83
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	5.25
P11 cycles	5.25
P12 cycles	9.83
P13 cycles	9.50
P14 cycles	9.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	3.78
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	47.82
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	47.46
Vectorization ratio load	72.22
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	69.23
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.19
Vector-efficiency ratio load	84.72
Vector-efficiency ratio store	83.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	84.62
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	42.31

Metric	Value
CQA speedup if no scalar integer	1.26
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.13
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	10.94
CQA cycles if fully vectorized	9.13
Front-end cycles	11.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	6.92
P3 cycles	6.92
P4 cycles	6.83
P5 cycles	6.83
P6 cycles	6.75
P7 cycles	6.75
P8 cycles	5.25
P9 cycles	5.25
P10 cycles	5.25
P11 cycles	5.25
P12 cycles	9.83
P13 cycles	9.50
P14 cycles	9.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	3.78
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	21.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	47.82
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	168.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	47.46
Vectorization ratio load	72.22
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	69.23
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.19
Vector-efficiency ratio load	84.72
Vector-efficiency ratio store	83.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	84.62
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	42.31

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 8.83 cycles (1.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.13 to 9.12 cycles (1.22x speedup).

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
69% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 21 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes. The binary loop is storing 168 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	6.92	6.92	6.83	6.83	6.75	6.75	5.25	5.25	5.25	5.25	9.83	9.50	9.67	0.00	0.00
cycles	4.50	4.50	6.92	6.92	6.83	6.83	6.75	6.75	5.25	5.25	5.25	5.25	9.83	9.50	9.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.13

Vectorization ratios

INT

all	40%
load	72%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	75%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	72%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	69%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.13 cycles. At this rate:

34% of peak load performance is reached (32.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40da58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W20, [X12, X10,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40da58 <advanceVelocity._omp_fn.0+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X16, X8, [X5, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
ADD X18, X16, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X8, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40da78 <advanceVelocity._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X3, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X8, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X16, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X6, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X18, X16, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X18, X17, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 40da78 <advanceVelocity._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W21, W20, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, #3841	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X19, #43691	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X11, W21, W14, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVK X19, #2730	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X11, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X2, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X5, X4, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X7, X5, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X17, X9, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d960 <advanceVelocity._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d930 <advanceVelocity._omp_fn.0+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d908 <advanceVelocity._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q0, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X18, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X6, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q3, Q2, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q21, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q20, [X16, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V1.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V20.2D, V30.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q20, [X16, X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q1, Q0, [X18, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
LDR Q22, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q6, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q7, Q23, [X1], #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V18.2D, V30.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V19.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V6.2D, V30.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q6, Q19, [X0, #2000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
LDR Q16, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q4, Q25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q5, Q17, [X1], #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V24.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V30.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V30.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q4, Q25, [X0, #2000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40da14 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W20, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
TBZ W20, #0, 40da58 <advanceVelocity._omp_fn.0+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W11, W10,LSL #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SMADDL X5, W20, W15, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D27, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X7, X16, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D20, D31, D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D20, [X16, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D3, D28, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMADD D6, D31, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D6, [X7, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D1, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D0, D31, D1, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D0, [X7, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X10, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X3, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W30, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40d850 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 8.83 cycles (1.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
69% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 21 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

21: addition or subtraction (all inside FMA instructions)
21: multiply (all inside FMA instructions)

The binary loop is loading 364 bytes. The binary loop is storing 168 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	6.92	6.92	6.83	6.83	6.75	6.75	5.25	5.25	5.25	5.25	9.83	9.50	9.67	0.00	0.00
cycles	4.50	4.50	6.92	6.92	6.83	6.83	6.75	6.75	5.25	5.25	5.25	5.25	9.83	9.50	9.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.13

Vectorization ratios

INT

all	40%
load	72%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	75%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	72%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	69%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.13 cycles. At this rate:

34% of peak load performance is reached (32.72 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40da58

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W20, [X12, X10,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40da58 <advanceVelocity._omp_fn.0+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X13, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X16, X8, [X5, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
ADD X18, X16, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X8, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W20, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40da78 <advanceVelocity._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X7, X3, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X8, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X16, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X8, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X6, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X18, X16, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X18, X17, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 40da78 <advanceVelocity._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W21, W20, #1, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, #3841	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X19, #43691	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X11, W21, W14, X18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MOVK X19, #2730	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X11, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X2, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X5, X4, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MADD X7, X5, X19, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X17, X9, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d960 <advanceVelocity._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d930 <advanceVelocity._omp_fn.0+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X17, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40d908 <advanceVelocity._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q1, Q0, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X18, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X6, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q3, Q2, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR Q21, [X8, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q20, [X16, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V1.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V20.2D, V30.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q20, [X16, X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q1, Q0, [X18, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
LDR Q22, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q6, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q7, Q23, [X1], #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V18.2D, V30.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V19.2D, V30.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V6.2D, V30.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STUR Q18, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q6, Q19, [X0, #2000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
LDR Q16, [X1, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q4, Q25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X0, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q5, Q17, [X1], #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V24.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V30.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V30.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STUR Q24, [X0, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
STP Q4, Q25, [X0, #2000]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40da14 <advanceVelocity._omp_fn.0+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W11, W20, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
TBZ W20, #0, 40da58 <advanceVelocity._omp_fn.0+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W11, W10,LSL #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
SMADDL X5, W20, W15, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDR D27, [X8, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X7, X16, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X16, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D20, D31, D27, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D20, [X16, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D3, D28, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMADD D6, D31, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D6, [X7, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D1, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D0, D31, D1, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D0, [X7, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X10, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X3, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W30, W10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40d850 <advanceVelocity._omp_fn.0+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code