OV - exec - Loop 132

	Loop Id: 132	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 11.69%

0x40b180 ADD	X4, X5, X5,LSL #1

0x40b184 ORN	W1, WZR, W10

0x40b188 LDR	X24, [X7, #24]

0x40b18c ADD	W2, W1, W6

0x40b190 AND	W3, W2, #0

0x40b194 ADD	X0, X24, X4

0x40b198 ADD	X25, X24, X9

0x40b19c LDR	D28, [X24, X4]

0x40b1a0 LDP	D29, D30, [X0, #8]

0x40b1a4 LDP	D17, D18, [X25, #8]

0x40b1a8 LDR	D0, [X24, X9]

0x40b1ac FSUB	D1, D29, S17

0x40b1b0 FSUB	D4, D30, S18

0x40b1b4 FSUB	D2, D28, S0

0x40b1b8 FMUL	D3, D1, D1

0x40b1bc FMADD	D5, D2, D2, D3

0x40b1c0 FMADD	D6, D4, D4, D5

0x40b1c4 FCMPE	D6, #0

0x40b1c8 FCCMPE	D27, D6, #1, #12

0x40b1cc CSINC	W26, WZR, WZR, #11

0x40b1d0 CBNZ	W26, 40b390

0x40b1d4 ADD	W2, W10, #1

0x40b1d8 ADD	X1, X25, #24

0x40b1dc CMP	W6, W2

0x40b1e0 B.LE	40b31c

0x40b1e4 CBZ	W3, 40b284

0x40b1e8 LDP	D31, D30, [X0, #8]

0x40b1ec LDP	D29, D17, [X1, #8]

0x40b1f0 LDR	D0, [X24, X4]

0x40b1f4 LDR	D18, [X25, #24]

0x40b1f8 FSUB	D3, D31, S29

0x40b1fc FSUB	D5, D30, S17

0x40b200 FSUB	D6, D0, S18

0x40b204 FMUL	D16, D3, D3

0x40b208 FMADD	D2, D6, D6, D16

0x40b20c FMADD	D7, D5, D5, D2

0x40b210 FCMPE	D7, #0

0x40b214 FCCMPE	D27, D7, #1, #12

0x40b218 CSINC	W3, WZR, WZR, #11

0x40b21c CBNZ	W3, 40b3f0

0x40b220 ADD	W2, W2, #1

0x40b224 ADD	X1, X1, #24

0x40b228 CMP	W6, W2

0x40b22c B.GT	40b284

0x40b230 B	40b31c

  (133) 0x40b234 ADD	X3, X1, #24

  (133) 0x40b238 LDP	D0, D29, [X0]

  (133) 0x40b23c ADD	W2, W2, #1

  (133) 0x40b240 LDP	D31, D17, [X3, #8]

  (133) 0x40b244 LDR	D16, [X1, #24]

  (133) 0x40b248 LDR	D30, [X0, #16]

  (133) 0x40b24c FSUB	D18, D29, S31

  (133) 0x40b250 FSUB	D4, D0, S16

  (133) 0x40b254 FSUB	D1, D30, S17

  (133) 0x40b258 FMUL	D7, D18, D18

  (133) 0x40b25c FMADD	D28, D4, D4, D7

  (133) 0x40b260 FMADD	D3, D1, D1, D28

  (133) 0x40b264 FCMPE	D3, #0

  (133) 0x40b268 FCCMPE	D27, D3, #1, #12

  (133) 0x40b26c CSINC	W1, WZR, WZR, #11

  (133) 0x40b270 CBNZ	W1, 40b330

  (133) 0x40b274 ADD	W2, W2, #1

  (133) 0x40b278 ADD	X1, X3, #24

  (133) 0x40b27c CMP	W6, W2

  (133) 0x40b280 B.LE	40b31c

  (133) 0x40b284 LDP	D0, D29, [X0]

  (133) 0x40b288 LDP	D31, D30, [X1]

  (133) 0x40b28c LDR	D7, [X0, #16]

  (133) 0x40b290 LDR	D18, [X1, #16]

  (133) 0x40b294 FSUB	D2, D29, S30

  (133) 0x40b298 FSUB	D28, D0, S31

  (133) 0x40b29c FSUB	D6, D7, S18

  (133) 0x40b2a0 FMUL	D17, D2, D2

  (133) 0x40b2a4 FMADD	D16, D28, D28, D17

  (133) 0x40b2a8 FMADD	D1, D6, D6, D16

  (133) 0x40b2ac FCMPE	D1, #0

  (133) 0x40b2b0 FCCMPE	D27, D1, #1, #12

  (133) 0x40b2b4 CSINC	W3, WZR, WZR, #11

  (133) 0x40b2b8 CBZ	W3, 40b234

  (133) 0x40b2bc FDIV	D4, D24, D1

  (133) 0x40b2c0 LDP	X24, X25, [X7, #40]

  (133) 0x40b2c4 LDR	D3, [X25, X5]

  (133) 0x40b2c8 ADD	X26, X24, X4

  (133) 0x40b2cc FMUL	D5, D4, D4

  (133) 0x40b2d0 FMUL	D0, D21, D4

  (133) 0x40b2d4 FMUL	D29, D23, D4

  (133) 0x40b2d8 FMUL	D31, D5, D0

  (133) 0x40b2dc FMADD	D30, D31, D19, D20

  (133) 0x40b2e0 FSUB	D17, D31, S24

  (133) 0x40b2e4 FNMSUB	D16, D17, D31, D22

  (133) 0x40b2e8 FMUL	D7, D30, D31

  (133) 0x40b2ec FMADD	D18, D16, D25, D3

  (133) 0x40b2f0 FMADD	D26, D16, D25, D26

  (133) 0x40b2f4 FMUL	D1, D7, D29

  (133) 0x40b2f8 STR	D18, [X25, X5]

  (133) 0x40b2fc LDR	D4, [X24, X4]

  (133) 0x40b300 FMSUB	D28, D1, D28, D4

  (133) 0x40b304 STR	D28, [X24, X4]

  (133) 0x40b308 LDP	D3, D5, [X26, #8]

  (133) 0x40b30c FMSUB	D2, D1, D2, D3

  (133) 0x40b310 FMSUB	D6, D1, D6, D5

  (133) 0x40b314 STP	D2, D6, [X26, #8]

  (133) 0x40b318 B	40b234

0x40b31c ADD	W8, W8, #1

0x40b320 ADD	X5, X5, #8

0x40b324 CMP	W12, W8

0x40b328 B.GT	40b180

  (133) 0x40b330 FDIV	D5, D24, D3

  (133) 0x40b334 LDP	X24, X25, [X7, #40]

  (133) 0x40b338 LDR	D2, [X25, X5]

  (133) 0x40b33c ADD	X26, X24, X4

  (133) 0x40b340 FMUL	D6, D5, D5

  (133) 0x40b344 FMUL	D0, D21, D5

  (133) 0x40b348 FMUL	D29, D23, D5

  (133) 0x40b34c FMUL	D31, D6, D0

  (133) 0x40b350 FMADD	D17, D31, D19, D20

  (133) 0x40b354 FSUB	D30, D31, S24

  (133) 0x40b358 FNMSUB	D16, D30, D31, D22

  (133) 0x40b35c FMUL	D7, D17, D31

  (133) 0x40b360 FMADD	D28, D16, D25, D2

  (133) 0x40b364 FMADD	D26, D16, D25, D26

  (133) 0x40b368 FMUL	D3, D7, D29

  (133) 0x40b36c STR	D28, [X25, X5]

  (133) 0x40b370 LDR	D5, [X24, X4]

  (133) 0x40b374 FMSUB	D4, D3, D4, D5

  (133) 0x40b378 STR	D4, [X24, X4]

  (133) 0x40b37c LDP	D2, D6, [X26, #8]

  (133) 0x40b380 FMSUB	D18, D3, D18, D2

  (133) 0x40b384 FMSUB	D1, D3, D1, D6

  (133) 0x40b388 STP	D18, D1, [X26, #8]

  (133) 0x40b38c B	40b274

0x40b390 FDIV	D16, D24, D6

0x40b394 LDP	X2, X26, [X7, #40]

0x40b398 LDR	D7, [X26, X5]

0x40b39c ADD	X1, X2, X4

0x40b3a0 FMUL	D28, D16, D16

0x40b3a4 FMUL	D0, D21, D16

0x40b3a8 FMUL	D31, D23, D16

0x40b3ac FMUL	D29, D28, D0

0x40b3b0 FMADD	D30, D29, D19, D20

0x40b3b4 FSUB	D17, D29, S24

0x40b3b8 FNMSUB	D3, D17, D29, D22

0x40b3bc FMUL	D18, D30, D29

0x40b3c0 FMADD	D5, D3, D25, D7

0x40b3c4 FMADD	D26, D3, D25, D26

0x40b3c8 FMUL	D6, D18, D31

0x40b3cc STR	D5, [X26, X5]

0x40b3d0 LDR	D16, [X2, X4]

0x40b3d4 FMSUB	D2, D6, D2, D16

0x40b3d8 STR	D2, [X2, X4]

0x40b3dc LDP	D7, D28, [X1, #8]

0x40b3e0 FMSUB	D1, D6, D1, D7

0x40b3e4 FMSUB	D4, D6, D4, D28

0x40b3e8 STP	D1, D4, [X1, #8]

0x40b3ec B	40b1d4

0x40b3f0 FDIV	D28, D24, D7

0x40b3f4 LDP	X24, X25, [X7, #40]

0x40b3f8 LDR	D1, [X25, X5]

0x40b3fc ADD	X26, X24, X4

0x40b400 FMUL	D4, D28, D28

0x40b404 FMUL	D0, D21, D28

0x40b408 FMUL	D31, D23, D28

0x40b40c FMUL	D30, D4, D0

0x40b410 FMADD	D29, D30, D19, D20

0x40b414 FSUB	D17, D30, S24

0x40b418 FNMSUB	D16, D17, D30, D22

0x40b41c FMUL	D18, D29, D30

0x40b420 FMADD	D2, D16, D25, D1

0x40b424 FMADD	D26, D16, D25, D26

0x40b428 FMUL	D7, D18, D31

0x40b42c STR	D2, [X25, X5]

0x40b430 LDR	D28, [X24, X4]

0x40b434 FMSUB	D6, D7, D6, D28

0x40b438 STR	D6, [X24, X4]

0x40b43c LDP	D1, D4, [X26, #8]

0x40b440 FMSUB	D3, D7, D3, D1

0x40b444 FMSUB	D5, D7, D5, D4

0x40b448 STP	D3, D5, [X26, #8]

0x40b44c B	40b220

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

[...]

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►98.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.03+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.95
CQA speedup if FP arith vectorized	1.73
CQA speedup if fully vectorized	1.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9, P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-178,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	7.94
Front-end cycles	12.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	3.08
P7 cycles	3.08
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 6.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	97.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	4.62
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.31
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	53.47
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	47.22
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	36.11

Metric	Value
CQA speedup if no scalar integer	1.95
CQA speedup if FP arith vectorized	1.73
CQA speedup if fully vectorized	1.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9, P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-178,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	7.94
Front-end cycles	12.13
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.17
P5 cycles	3.17
P6 cycles	3.08
P7 cycles	3.08
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 6.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	97.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	4.62
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.31
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.11
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	53.47
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	47.22
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	36.11

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178,187-191,197-216.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178,187,191,197-198,201,206-210,213-216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=30
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 30 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 6.67 cycles (1.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.00 to 7.94 cycles (1.64x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	97
loop length	388
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	3.25	3.25	3.17	3.17	3.08	3.08	13.00	13.00	13.00	13.00	7.67	7.67	7.67	0.00	0.00
cycles	4.50	4.50	3.25	3.25	3.17	3.17	3.08	3.08	13.00	13.00	13.00	13.00	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-6.99

Cycles summary

Front-end	12.13
Overall L1	13.00

Vectorization ratios

INT

all	30%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	11%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

16% of peak load performance is reached (15.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X4, X5, X5,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORN W1, WZR, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [X7, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W2, W1, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
AND W3, W2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X24, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X24, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D29, D30, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D17, D18, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X24, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D1, D29, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D4, D30, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D2, D28, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D3, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D5, D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D6, D4, D4, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D27, D6, #1, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W26, WZR, WZR, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ W26, 40b390 <ljForce._omp_fn.1+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X25, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40b31c <ljForce._omp_fn.1+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W3, 40b284 <ljForce._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D31, D30, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D29, D17, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D3, D31, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D5, D30, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D6, D0, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D16, D3, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D6, D6, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D7, D5, D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D27, D7, #1, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W3, WZR, WZR, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CBNZ W3, 40b3f0 <ljForce._omp_fn.1+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b284 <ljForce._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b31c <ljForce._omp_fn.1+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W12, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b180 <ljForce._omp_fn.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D16, D24, D6	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X2, X26, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR D7, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X1, X2, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D28, D16, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D0, D21, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D23, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D29, D28, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D30, D29, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D17, D29, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D3, D17, D29, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D30, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D5, D3, D25, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D26, D3, D25, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D6, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D5, [X26, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D16, [X2, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D2, D6, D2, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D2, [X2, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D7, D28, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D1, D6, D1, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D4, D6, D4, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D1, D4, [X1, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b1d4 <ljForce._omp_fn.1+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D28, D24, D7	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X24, X25, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR D1, [X25, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X26, X24, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D4, D28, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D0, D21, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D23, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D30, D4, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D29, D30, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D17, D30, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D16, D17, D30, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D29, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D16, D25, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D26, D16, D25, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D2, [X25, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D28, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D6, D7, D6, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D6, [X24, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D1, D4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D3, D7, D3, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D5, D7, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D3, D5, [X26, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b220 <ljForce._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=30
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 6.67 cycles (1.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	97
loop length	388
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	3.25	3.25	3.17	3.17	3.08	3.08	13.00	13.00	13.00	13.00	7.67	7.67	7.67	0.00	0.00
cycles	4.50	4.50	3.25	3.25	3.17	3.17	3.08	3.08	13.00	13.00	13.00	13.00	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-6.99

Cycles summary

Front-end	12.13
Overall L1	13.00

Vectorization ratios

INT

all	30%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	11%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

16% of peak load performance is reached (15.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.92 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X4, X5, X5,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORN W1, WZR, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X24, [X7, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD W2, W1, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
AND W3, W2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X24, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X24, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D28, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D29, D30, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D17, D18, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X24, X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D1, D29, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D4, D30, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D2, D28, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D3, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D5, D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D6, D4, D4, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D27, D6, #1, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W26, WZR, WZR, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ W26, 40b390 <ljForce._omp_fn.1+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X25, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40b31c <ljForce._omp_fn.1+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W3, 40b284 <ljForce._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D31, D30, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D29, D17, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D3, D31, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D5, D30, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D6, D0, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D16, D3, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D6, D6, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D7, D5, D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D27, D7, #1, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W3, WZR, WZR, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CBNZ W3, 40b3f0 <ljForce._omp_fn.1+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W6, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b284 <ljForce._omp_fn.1+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b31c <ljForce._omp_fn.1+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W12, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b180 <ljForce._omp_fn.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D16, D24, D6	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X2, X26, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR D7, [X26, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X1, X2, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D28, D16, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D0, D21, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D23, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D29, D28, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D30, D29, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D17, D29, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D3, D17, D29, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D30, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D5, D3, D25, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D26, D3, D25, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D6, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D5, [X26, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D16, [X2, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D2, D6, D2, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D2, [X2, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D7, D28, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D1, D6, D1, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D4, D6, D4, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D1, D4, [X1, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b1d4 <ljForce._omp_fn.1+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D28, D24, D7	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X24, X25, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR D1, [X25, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X26, X24, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D4, D28, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D0, D21, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D23, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D30, D4, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D29, D30, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D17, D30, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D16, D17, D30, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D29, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D16, D25, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D26, D16, D25, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D18, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D2, [X25, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D28, [X24, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D6, D7, D6, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D6, [X24, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D1, D4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D3, D7, D3, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D5, D7, D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D3, D5, [X26, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b220 <ljForce._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code