OV - exec - Loop 119

	Loop Id: 119	Module: exec	Source: linkCells.c:211-385 [...]	Coverage: 0.26%

  (118) 0x40a628 UBFM	X25, X23, #62, #31

  (118) 0x40a62c ORR	W20, WZR, W23

  (118) 0x40a630 LDR	W4, [X5, X25]

  (118) 0x40a634 UBFM	W19, W23, #26, #25

  (118) 0x40a638 CMP	W4, #0

  (118) 0x40a63c B.LE	40a818

0x40a640 LDR	D29, [X21, #64]

0x40a644 MOVZ	W22, #0

0x40a648 ORR	W24, WZR, W19

0x40a64c LDP	D31, D30, [X21, #48]

0x40a650 LDR	X3, [X27, #24]

0x40a654 LDP	W2, W0, [X21]

0x40a658 LDR	W1, [X21, #8]

0x40a65c HINT	#0

0x40a660 UMADDL	X6, W24, W26, XZR

0x40a664 ORR	W11, WZR, W2

0x40a668 LDR	D4, [X3, X6]

0x40a66c ADD	X7, X3, X6

0x40a670 LDP	D27, D26, [X7, #8]

0x40a674 FCMPE	D4, D31

0x40a678 B.GE	40a69c

0x40a67c LDR	D3, [X21, #24]

0x40a680 LDR	D2, [X21, #96]

0x40a684 FSUB	D0, D4, S3

0x40a688 FMUL	D1, D0, D2

0x40a68c FCVTMS	W8, D1

0x40a690 CMP	W8, W2

0x40a694 CSINC	W9, WZR, WZR, #1

0x40a698 SUB	W11, W8, W9

0x40a69c FCMPE	D27, D30

0x40a6a0 ORR	W13, WZR, W0

0x40a6a4 B.GE	40a6c8

0x40a6a8 LDR	D5, [X21, #32]

0x40a6ac LDR	D6, [X21, #104]

0x40a6b0 FSUB	D7, D27, S5

0x40a6b4 FMUL	D16, D7, D6

0x40a6b8 FCVTMS	W10, D16

0x40a6bc CMP	W10, W0

0x40a6c0 CSINC	W12, WZR, WZR, #1

0x40a6c4 SUB	W13, W10, W12

0x40a6c8 FCMPE	D26, D29

0x40a6cc B.GE	40a790

0x40a6d0 LDR	D25, [X21, #40]

0x40a6d4 LDR	D28, [X21, #112]

0x40a6d8 FSUB	D17, D26, S25

0x40a6dc FMUL	D18, D17, D28

0x40a6e0 FCVTMS	W10, D18

0x40a6e4 CMP	W10, W1

0x40a6e8 CSINC	W12, WZR, WZR, #1

0x40a6ec SUB	W14, W10, W12

0x40a6f0 CMN	W14, #1

0x40a6f4 B.EQ	40a7c4

0x40a6f8 CMP	W13, W0

0x40a6fc B.EQ	40a7f0

0x40a700 CMN	W13, #1

0x40a704 B.EQ	40a840

0x40a708 CMP	W11, W2

0x40a70c B.EQ	40a860

0x40a710 CMN	W11, #1

0x40a714 B.EQ	40a874

0x40a718 MADD	W11, W13, W2, W11

0x40a71c MADD	W13, W0, W2, WZR

0x40a720 MADD	W4, W13, W14, W11

0x40a724 TBNZ	W4, #31, 40a884

0x40a728 LDR	W13, [X21, #20]

0x40a72c CMP	W4, W13

0x40a730 B.GE	40a8a4

0x40a734 CMP	W4, W23

0x40a738 B.EQ	40a778

0x40a73c ORR	X1, XZR, X27

0x40a740 ORR	W3, WZR, W20

0x40a744 ORR	W2, WZR, W22

0x40a748 ORR	X0, XZR, X21

0x40a74c BL	40a420

0x40a750 LDR	X5, [X21, #120]

0x40a754 LDR	W1, [X5, X25]

0x40a758 CMP	W1, W22

0x40a75c B.LE	40a814

0x40a760 LDR	X3, [X27, #24]

0x40a764 LDR	D29, [X21, #64]

0x40a768 LDP	D31, D30, [X21, #48]

0x40a76c LDP	W2, W0, [X21]

0x40a770 LDR	W1, [X21, #8]

0x40a774 B	40a660

0x40a778 LDR	W11, [X5, X25]

0x40a77c ADD	W22, W22, #1

0x40a780 CMP	W11, W22

0x40a784 B.LE	40a814

0x40a788 ADD	W24, W19, W22

0x40a78c B	40a660

0x40a790 LDR	W4, [X21, #12]

0x40a794 ADD	W15, W2, #2

0x40a798 MADD	W14, W1, W0, WZR

0x40a79c ADD	W16, W0, #2

0x40a7a0 ADD	W17, W11, #1

0x40a7a4 MADD	W18, W15, W1, WZR

0x40a7a8 MADD	W30, W13, W15, W15

0x40a7ac ADD	W6, W4, W14,LSL #1

0x40a7b0 ADD	W7, W6, W18,LSL #1

0x40a7b4 MADD	W8, W16, W15, W7

0x40a7b8 ADD	W9, W8, W30

0x40a7bc ADD	W4, W9, W17

0x40a7c0 B	40a724

0x40a7c4 LDR	W8, [X21, #12]

0x40a7c8 ADD	W30, W2, #2

0x40a7cc MADD	W18, W1, W0, WZR

0x40a7d0 ADD	W6, W11, #1

0x40a7d4 MADD	W4, W30, W1, WZR

0x40a7d8 MADD	W7, W13, W30, W30

0x40a7dc ADD	W9, W8, W18,LSL #1

0x40a7e0 ADD	W10, W9, W4,LSL #1

0x40a7e4 ADD	W12, W10, W7

0x40a7e8 ADD	W4, W12, W6

0x40a7ec B	40a724

0x40a7f0 LDR	W15, [X21, #12]

0x40a7f4 MADD	W12, W1, W0, WZR

0x40a7f8 ADD	W13, W2, #2

0x40a7fc ADD	W11, W11, #1

0x40a800 ADD	W16, W15, W12,LSL #1

0x40a804 MADD	W17, W13, W1, W16

0x40a808 MADD	W14, W14, W13, W17

0x40a80c ADD	W4, W14, W11

0x40a810 B	40a724

0x40a814 LDR	W2, [X21, #12]

  (118) 0x40a818 ADD	X23, X23, #1

  (118) 0x40a81c CMP	W2, W23

  (118) 0x40a820 B.GT	40a628

0x40a860 LDR	W17, [X21, #12]

0x40a864 MADD	W18, W1, W0, W17

0x40a868 MADD	W30, W14, W0, W18

0x40a86c ADD	W4, W30, W13

0x40a870 B	40a724

0x40a874 LDR	W15, [X21, #12]

0x40a878 MADD	W16, W14, W0, W15

0x40a87c ADD	W4, W16, W13

0x40a880 B	40a724

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

385:       boxes->nAtoms[ii] = 0;

Coverage (%)	Name	Source Location	Module
►99.01+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.64
CQA speedup if FP arith vectorized	1.21
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6,
Function	updateLinkCells
Source	linkCells.c:211-212,linkCells.c:215-218,linkCells.c:221-224,linkCells.c:227-227,linkCells.c:232-234,linkCells.c:237-239,linkCells.c:244-247,linkCells.c:291-291,linkCells.c:294-301,linkCells.c:352-354,linkCells.c:359-361,linkCells.c:364-367,linkCells.c:370-373
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	10.50
Front-end cycles	15.75
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	9.83
P3 cycles	9.75
P4 cycles	9.83
P5 cycles	9.83
P6 cycles	17.00
P7 cycles	9.75
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	127.00
Nb uops	126.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.35
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	204.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.80
Vectorization ratio load	13.04
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.76
Vector-efficiency ratio load	46.74
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	30.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.41

Metric	Value
CQA speedup if no scalar integer	3.64
CQA speedup if FP arith vectorized	1.21
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6,
Function	updateLinkCells
Source	linkCells.c:211-212,linkCells.c:215-218,linkCells.c:221-224,linkCells.c:227-227,linkCells.c:232-234,linkCells.c:237-239,linkCells.c:244-247,linkCells.c:291-291,linkCells.c:294-301,linkCells.c:352-354,linkCells.c:359-361,linkCells.c:364-367,linkCells.c:370-373
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.00
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	10.50
Front-end cycles	15.75
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	9.83
P3 cycles	9.75
P4 cycles	9.83
P5 cycles	9.83
P6 cycles	17.00
P7 cycles	9.75
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	9.33
P13 cycles	9.33
P14 cycles	9.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	127.00
Nb uops	126.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.35
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	204.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.80
Vectorization ratio load	13.04
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.76
Vector-efficiency ratio load	46.74
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	30.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	updateLinkCells
Source file and lines	linkCells.c:211-385
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,291-301,352-373,385.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-212,215-218,221-224,227,232-234,237-239,244-247,291,294-301,352-354,359-361,364-367,370-373.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 4.67 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 10.50 cycles (1.62x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

13% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 0.50 cycles (34.00x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTMS: 3 occurrences►
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 204 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	127
loop length	508
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.50	10.50	9.83	9.75	9.83	9.83	17.00	9.75	3.00	3.00	3.00	3.00	9.33	9.33	9.33	0.00	0.00
cycles	10.50	10.50	9.83	9.75	9.83	9.83	17.00	9.75	3.00	3.00	3.00	3.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

INT

all	4%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40a724

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D29, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ W22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W24, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D31, D30, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X3, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W2, W0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																					N/A
UMADDL X6, W24, W26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR W11, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D4, [X3, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X7, X3, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D27, D26, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40a69c <updateLinkCells+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D0, D4, S3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D1, D0, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W8, D1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W8, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W9, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W11, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FCMPE D27, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ORR W13, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 40a6c8 <updateLinkCells+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D6, [X21, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D7, D27, S5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D16, D7, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W10, D16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W10, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W12, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W13, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMPE D26, D29	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40a790 <updateLinkCells+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D28, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D17, D26, S25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W10, D18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W10, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W12, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W14, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMN W14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a7c4 <updateLinkCells+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W13, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a7f0 <updateLinkCells+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a840 <updateLinkCells+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a860 <updateLinkCells+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a874 <updateLinkCells+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W11, W13, W2, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W13, W0, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD W4, W13, W14, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
TBNZ W4, #31, 40a884 <updateLinkCells+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W13, [X21, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W4, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8a4 <updateLinkCells+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W4, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a778 <updateLinkCells+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W3, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 40a420 <moveAtom>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W1, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a814 <updateLinkCells+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D31, D30, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP W2, W0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 40a660 <updateLinkCells+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a814 <updateLinkCells+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W24, W19, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40a660 <updateLinkCells+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W15, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W14, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W15, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W13, W15, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W4, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W7, W6, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W8, W16, W15, W7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W9, W8, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W9, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W30, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W4, W30, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD W7, W13, W30, W30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W8, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W9, W4,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W12, W10, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W12, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W15, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W12, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W13, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W16, W15, W12,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W17, W13, W1, W16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W14, W14, W13, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W14, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W17, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W18, W1, W0, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W14, W0, W18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W30, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W15, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W16, W14, W0, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W4, W16, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	updateLinkCells
Source file and lines	linkCells.c:211-385
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 4.67 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

13% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 0.50 cycles (34.00x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTMS: 3 occurrences►
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 204 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	127
loop length	508
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.50	10.50	9.83	9.75	9.83	9.83	17.00	9.75	3.00	3.00	3.00	3.00	9.33	9.33	9.33	0.00	0.00
cycles	10.50	10.50	9.83	9.75	9.83	9.83	17.00	9.75	3.00	3.00	3.00	3.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.75
Overall L1	17.00

Vectorization ratios

INT

all	4%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40a724

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D29, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ W22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W24, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D31, D30, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X3, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W2, W0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
HINT #0																					N/A
UMADDL X6, W24, W26, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ORR W11, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D4, [X3, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X7, X3, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D27, D26, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMPE D4, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40a69c <updateLinkCells+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D3, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D0, D4, S3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D1, D0, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W8, D1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W8, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W9, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W11, W8, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FCMPE D27, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ORR W13, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 40a6c8 <updateLinkCells+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D6, [X21, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D7, D27, S5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D16, D7, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W10, D16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W10, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W12, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W13, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FCMPE D26, D29	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40a790 <updateLinkCells+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D28, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FSUB D17, D26, S25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCVTMS W10, D18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	1	scal (50.0%)
CMP W10, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC W12, WZR, WZR, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W14, W10, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMN W14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a7c4 <updateLinkCells+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W13, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a7f0 <updateLinkCells+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a840 <updateLinkCells+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W11, W2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a860 <updateLinkCells+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a874 <updateLinkCells+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W11, W13, W2, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W13, W0, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD W4, W13, W14, W11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
TBNZ W4, #31, 40a884 <updateLinkCells+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W13, [X21, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W4, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a8a4 <updateLinkCells+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W4, W23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a778 <updateLinkCells+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W3, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 40a420 <moveAtom>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W1, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a814 <updateLinkCells+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D31, D30, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP W2, W0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 40a660 <updateLinkCells+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W11, [X5, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W22, W22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a814 <updateLinkCells+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W24, W19, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40a660 <updateLinkCells+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W4, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W15, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W14, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W17, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W15, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W13, W15, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W4, W14,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W7, W6, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W8, W16, W15, W7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W9, W8, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W9, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W30, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W6, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W4, W30, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD W7, W13, W30, W30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W9, W8, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W10, W9, W4,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W12, W10, W7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W12, W6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W15, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W12, W1, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W13, W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W16, W15, W12,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W17, W13, W1, W16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W14, W14, W13, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W14, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W2, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W17, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W18, W1, W0, W17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W14, W0, W18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W30, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W15, [X21, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W16, W14, W0, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W4, W16, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40a724 <updateLinkCells+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code