OV - exec - Function kineticEnergy._omp

	Function: kineticEnergy._omp_fn.0	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.09% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x40dc40 STP	X29, X30, [SP, #960]!

0x40dc44 ADD	X29, SP, #0

0x40dc48 STP	X19, X20, [SP, #16]

0x40dc4c ORR	X20, XZR, X0

0x40dc50 STP	X21, X22, [SP, #32]

0x40dc54 LDR	X19, [X0]

0x40dc58 STR	X23, [SP, #48]

0x40dc5c BL	402640

0x40dc60 ORR	W21, WZR, W0

0x40dc64 BL	402660

0x40dc68 LDR	X23, [X19, #24]

0x40dc6c ORR	W8, WZR, W0

0x40dc70 LDR	W22, [X23, #12]

0x40dc74 SDIV	W14, W22, W21

0x40dc78 MSUB	W0, W14, W21, W22

0x40dc7c CMP	W8, W0

0x40dc80 B.LT	40e058

0x40dc84 MADD	W1, W14, W8, W0

0x40dc88 MOVI	D7, #0

0x40dc8c ADD	W17, W14, W1

0x40dc90 CMP	W1, W17

0x40dc94 B.GE	40e018

0x40dc98 LDR	X15, [X23, #120]

0x40dc9c FMOV	D6, #0.5000000

0x40dca0 MOVI	V5.2D, #0

0x40dca4 SBFM	X8, X1, #0, #31

0x40dca8 MOVZ	W16, #24

0x40dcac FMOV	V16.2D, #0.5000000

    (152) 0x40dcb0 LDR	W11, [X15, X8,LSL #2]

    (152) 0x40dcb4 UBFM	W9, W8, #26, #25

    (152) 0x40dcb8 CMP	W11, #0

    (152) 0x40dcbc B.LE	40e00c

    (152) 0x40dcc0 LDP	X2, X12, [X19, #32]

    (152) 0x40dcc4 SUB	W3, W11, #1

    (152) 0x40dcc8 LDR	X18, [X2, #16]

    (152) 0x40dccc LDR	X10, [X2, #32]

    (152) 0x40dcd0 CMP	W3, #6

    (152) 0x40dcd4 B.LS	40e050

    (152) 0x40dcd8 ADD	X13, X8, X8,LSL #1

    (152) 0x40dcdc UBFM	X7, X8, #56, #55

    (152) 0x40dce0 UBFM	W4, W11, #2, #31

    (152) 0x40dce4 MOVI	V0.2D, #0

    (152) 0x40dce8 ADD	X5, X18, X7

    (152) 0x40dcec ADD	X30, X12, #8

    (152) 0x40dcf0 ADD	X21, X5, W4,UXTW #4

    (152) 0x40dcf4 ADD	X14, X10, X13,LSL #9

    (152) 0x40dcf8 ORR	X22, XZR, X5

    (152) 0x40dcfc TBZ	W4, #0, 40dd80

    (152) 0x40dd00 LD3	{V25.2D, V26.2D, V27.2D}, [X14]

    (152) 0x40dd04 ADD	X23, X14, #48

    (152) 0x40dd08 ADD	X22, X5, #16

    (152) 0x40dd0c ORR	V0.16B, V5.16B, V5.16B

    (152) 0x40dd10 ADD	X14, X14, #96

    (152) 0x40dd14 LD3	{V28.2D, V29.2D, V30.2D}, [X23]

    (152) 0x40dd18 LDR	W0, [X18, X7]

    (152) 0x40dd1c ADD	X1, X30, W0,SXTW #4

    (152) 0x40dd20 LDR	D22, [X1]

    (152) 0x40dd24 LDP	W3, W2, [X5, #4]

    (152) 0x40dd28 ADD	X6, X30, W2,SXTW #4

    (152) 0x40dd2c ADD	X7, X30, W3,SXTW #4

    (152) 0x40dd30 FMUL	V23.2D, V26.2D, V26.2D

    (152) 0x40dd34 LDR	D24, [X6]

    (152) 0x40dd38 LD1	{V22.D[1]}, [X7]

    (152) 0x40dd3c FMUL	V31.2D, V29.2D, V29.2D

    (152) 0x40dd40 LDR	W13, [X5, #12]

    (152) 0x40dd44 ADD	X4, X30, W13,SXTW #4

    (152) 0x40dd48 FMLA	V23.2D, V25.2D, V25.2D

    (152) 0x40dd4c LD1	{V24.D[1]}, [X4]

    (152) 0x40dd50 FMLA	V31.2D, V28.2D, V28.2D

    (152) 0x40dd54 FMLA	V23.2D, V27.2D, V27.2D

    (152) 0x40dd58 FDIV	V1.2D, V16.2D, V22.2D

    (152) 0x40dd5c FMLA	V31.2D, V30.2D, V30.2D

    (152) 0x40dd60 FDIV	V2.2D, V16.2D, V24.2D

    (152) 0x40dd64 FMLA	V0.2D, V1.2D, V23.2D

    (152) 0x40dd68 FMLA	V0.2D, V2.2D, V31.2D

    (152) 0x40dd6c CMP	X21, X22

    (152) 0x40dd70 B.EQ	40de54

    (152) 0x40dd74 HINT	#0

    (152) 0x40dd78 HINT	#0

    (152) 0x40dd7c HINT	#0

      (154) 0x40dd80 ADD	X23, X14, #48

      (154) 0x40dd84 LDP	W1, W2, [X22]

      (154) 0x40dd88 ADD	X7, X30, W1,SXTW #4

      (154) 0x40dd8c ADD	X0, X14, #96

      (154) 0x40dd90 ADD	X6, X30, W2,SXTW #4

      (154) 0x40dd94 ADD	X5, X14, #144

      (154) 0x40dd98 ADD	X3, X22, #16

      (154) 0x40dd9c LD3	{V25.2D, V26.2D, V27.2D}, [X14]

      (154) 0x40dda0 ADD	X14, X14, #192

      (154) 0x40dda4 LD3	{V28.2D, V29.2D, V30.2D}, [X23]

      (154) 0x40dda8 LD3	{V19.2D, V20.2D, V21.2D}, [X0]

      (154) 0x40ddac LD3	{V22.2D, V23.2D, V24.2D}, [X5]

      (154) 0x40ddb0 LDR	D4, [X7]

      (154) 0x40ddb4 FMUL	V3.2D, V26.2D, V26.2D

      (154) 0x40ddb8 LDP	W13, W4, [X22, #8]

      (154) 0x40ddbc ADD	X23, X30, W13,SXTW #4

      (154) 0x40ddc0 ADD	X1, X30, W4,SXTW #4

      (154) 0x40ddc4 FMUL	V26.2D, V29.2D, V29.2D

      (154) 0x40ddc8 LDR	W22, [X22, #16]

      (154) 0x40ddcc ADD	X0, X30, W22,SXTW #4

      (154) 0x40ddd0 LD1	{V4.D[1]}, [X6]

      (154) 0x40ddd4 FMLA	V3.2D, V25.2D, V25.2D

      (154) 0x40ddd8 ADD	X22, X3, #16

      (154) 0x40dddc LDR	D25, [X23]

      (154) 0x40dde0 FMUL	V18.2D, V20.2D, V20.2D

      (154) 0x40dde4 LDP	W5, W2, [X3, #4]

      (154) 0x40dde8 ADD	X7, X30, W2,SXTW #4

      (154) 0x40ddec ADD	X6, X30, W5,SXTW #4

      (154) 0x40ddf0 FMLA	V26.2D, V28.2D, V28.2D

      (154) 0x40ddf4 LDR	D29, [X7]

      (154) 0x40ddf8 FMLA	V3.2D, V27.2D, V27.2D

      (154) 0x40ddfc LDR	D27, [X0]

      (154) 0x40de00 FDIV	V17.2D, V16.2D, V4.2D

      (154) 0x40de04 LD1	{V25.D[1]}, [X1]

      (154) 0x40de08 FMLA	V26.2D, V30.2D, V30.2D

      (154) 0x40de0c LDR	W3, [X3, #12]

      (154) 0x40de10 ADD	X13, X30, W3,SXTW #4

      (154) 0x40de14 LD1	{V27.D[1]}, [X6]

      (154) 0x40de18 FMLA	V18.2D, V19.2D, V19.2D

      (154) 0x40de1c LD1	{V29.D[1]}, [X13]

      (154) 0x40de20 FMLA	V0.2D, V17.2D, V3.2D

      (154) 0x40de24 FDIV	V20.2D, V16.2D, V25.2D

      (154) 0x40de28 FMUL	V30.2D, V23.2D, V23.2D

      (154) 0x40de2c FMLA	V18.2D, V21.2D, V21.2D

      (154) 0x40de30 FDIV	V19.2D, V16.2D, V27.2D

      (154) 0x40de34 FMLA	V0.2D, V20.2D, V26.2D

      (154) 0x40de38 FDIV	V21.2D, V16.2D, V29.2D

      (154) 0x40de3c FMLA	V30.2D, V22.2D, V22.2D

      (154) 0x40de40 FMLA	V0.2D, V19.2D, V18.2D

      (154) 0x40de44 FMLA	V30.2D, V24.2D, V24.2D

      (154) 0x40de48 FMLA	V0.2D, V21.2D, V30.2D

      (154) 0x40de4c CMP	X21, X22

      (154) 0x40de50 B.NE	40dd80

    (152) 0x40de54 FADDP	D28, V0.2D

    (152) 0x40de58 FADD	D7, D7, D28

    (152) 0x40de5c ANDS	XZR, X11, #4160

    (152) 0x40de60 B.EQ	40e00c

    (155) 0x40de64 AND	W6, W11, #1886

    (155) 0x40de68 ADD	W9, W9, W6

    (155) 0x40de6c LDRSW	X30, [X18, X9,SXTW #2]

    (155) 0x40de70 SMADDL	X21, W9, W16, XZR

    (155) 0x40de74 ADD	W14, W6, #1

    (155) 0x40de78 SBFM	X9, X9, #62, #31

    (155) 0x40de7c ADD	X23, X10, X21

    (155) 0x40de80 LDR	D23, [X10, X21]

    (155) 0x40de84 ADD	X4, X12, X30,LSL #4

    (155) 0x40de88 LDP	D0, D31, [X23, #8]

    (155) 0x40de8c LDR	D2, [X4, #8]

    (155) 0x40de90 FMUL	D22, D0, D0

    (155) 0x40de94 FDIV	D3, D6, D2

    (155) 0x40de98 FMADD	D1, D23, D23, D22

    (155) 0x40de9c FMADD	D24, D31, D31, D1

    (155) 0x40dea0 FMADD	D7, D3, D24, D7

    (155) 0x40dea4 CMP	W14, W11

    (155) 0x40dea8 B.GE	40e00c

  (153) 0x40deac ADD	X18, X18, X9

  (153) 0x40deb0 ADD	X22, X21, #24

  (153) 0x40deb4 LDRSW	X5, [X18, #4]

  (153) 0x40deb8 ADD	X0, X10, X22

  (153) 0x40debc ADD	W1, W6, #2

  (153) 0x40dec0 LDP	D18, D4, [X0, #8]

  (153) 0x40dec4 LDR	D26, [X10, X22]

  (153) 0x40dec8 ADD	X2, X12, X5,LSL #4

  (153) 0x40decc LDR	D19, [X2, #8]

  (153) 0x40ded0 FMUL	D30, D18, D18

  (153) 0x40ded4 FMADD	D17, D26, D26, D30

  (153) 0x40ded8 FDIV	D29, D6, D19

  (153) 0x40dedc FMADD	D27, D4, D4, D17

  (153) 0x40dee0 FMADD	D7, D29, D27, D7

  (153) 0x40dee4 CMP	W11, W1

  (153) 0x40dee8 B.LE	40e00c

  (153) 0x40deec LDRSW	X14, [X18, #8]

  (153) 0x40def0 ADD	X13, X21, #48

  (153) 0x40def4 ADD	W3, W6, #3

  (153) 0x40def8 ADD	X30, X10, X13

  (153) 0x40defc LDR	D25, [X10, X13]

  (153) 0x40df00 LDP	D20, D21, [X30, #8]

  (153) 0x40df04 ADD	X9, X12, X14,LSL #4

  (153) 0x40df08 LDR	D31, [X9, #8]

  (153) 0x40df0c FMUL	D28, D20, D20

  (153) 0x40df10 FDIV	D22, D6, D31

  (153) 0x40df14 FMADD	D23, D25, D25, D28

  (153) 0x40df18 FMADD	D0, D21, D21, D23

  (153) 0x40df1c FMADD	D7, D22, D0, D7

  (153) 0x40df20 CMP	W11, W3

  (153) 0x40df24 B.LE	40e00c

  (153) 0x40df28 LDRSW	X0, [X18, #12]

  (153) 0x40df2c ADD	X23, X21, #72

  (153) 0x40df30 ADD	W22, W6, #4

  (153) 0x40df34 ADD	X4, X10, X23

  (153) 0x40df38 LDR	D1, [X10, X23]

  (153) 0x40df3c LDP	D24, D2, [X4, #8]

  (153) 0x40df40 ADD	X1, X12, X0,LSL #4

  (153) 0x40df44 LDR	D4, [X1, #8]

  (153) 0x40df48 FMUL	D3, D24, D24

  (153) 0x40df4c FDIV	D30, D6, D4

  (153) 0x40df50 FMADD	D26, D1, D1, D3

  (153) 0x40df54 FMADD	D18, D2, D2, D26

  (153) 0x40df58 FMADD	D7, D30, D18, D7

  (153) 0x40df5c CMP	W11, W22

  (153) 0x40df60 B.LE	40e00c

  (153) 0x40df64 LDRSW	X30, [X18, #16]

  (153) 0x40df68 ADD	X2, X21, #96

  (153) 0x40df6c ADD	W7, W6, #5

  (153) 0x40df70 ADD	X13, X10, X2

  (153) 0x40df74 LDR	D17, [X10, X2]

  (153) 0x40df78 LDP	D27, D19, [X13, #8]

  (153) 0x40df7c ADD	X14, X12, X30,LSL #4

  (153) 0x40df80 LDR	D21, [X14, #8]

  (153) 0x40df84 FMUL	D29, D27, D27

  (153) 0x40df88 FDIV	D28, D6, D21

  (153) 0x40df8c FMADD	D25, D17, D17, D29

  (153) 0x40df90 FMADD	D20, D19, D19, D25

  (153) 0x40df94 FMADD	D7, D28, D20, D7

  (153) 0x40df98 CMP	W11, W7

  (153) 0x40df9c B.LE	40e00c

  (153) 0x40dfa0 LDRSW	X22, [X18, #20]

  (153) 0x40dfa4 ADD	X3, X21, #120

  (153) 0x40dfa8 ADD	W6, W6, #6

  (153) 0x40dfac ADD	X23, X10, X3

  (153) 0x40dfb0 LDR	D23, [X10, X3]

  (153) 0x40dfb4 LDP	D0, D31, [X23, #8]

  (153) 0x40dfb8 ADD	X4, X12, X22,LSL #4

  (153) 0x40dfbc LDR	D2, [X4, #8]

  (153) 0x40dfc0 FMUL	D22, D0, D0

  (153) 0x40dfc4 FDIV	D3, D6, D2

  (153) 0x40dfc8 FMADD	D1, D23, D23, D22

  (153) 0x40dfcc FMADD	D24, D31, D31, D1

  (153) 0x40dfd0 FMADD	D7, D3, D24, D7

  (153) 0x40dfd4 CMP	W11, W6

  (153) 0x40dfd8 B.LE	40e00c

  (153) 0x40dfdc ADD	X11, X21, #144

  (153) 0x40dfe0 ADD	X21, X10, X11

  (153) 0x40dfe4 LDR	D26, [X10, X11]

  (153) 0x40dfe8 LDRSW	X10, [X18, #24]

  (153) 0x40dfec LDP	D18, D4, [X21, #8]

  (153) 0x40dff0 ADD	X12, X12, X10,LSL #4

  (153) 0x40dff4 LDR	D19, [X12, #8]

  (153) 0x40dff8 FMUL	D30, D18, D18

  (153) 0x40dffc FMADD	D17, D26, D26, D30

  (153) 0x40e000 FDIV	D29, D6, D19

  (153) 0x40e004 FMADD	D27, D4, D4, D17

  (153) 0x40e008 FMADD	D7, D27, D29, D7

    (152) 0x40e00c ADD	X8, X8, #1

    (152) 0x40e010 CMP	W17, W8

    (152) 0x40e014 B.GT	40dcb0

(156) 0x40e018 ADD	X20, X20, #8

(156) 0x40e01c LDR	X1, [X20]

  (151) 0x40e020 FMOV	D6, X1

  (151) 0x40e024 ORR	X19, XZR, X1

  (151) 0x40e028 FADD	D5, D7, D6

  (151) 0x40e02c FMOV	X17, D5

  (151) 0x40e030 CAS	X19, X17, [X20]

  (151) 0x40e034 CMP	X1, X19

  (151) 0x40e038 B.NE	40e064

(156) 0x40e03c LDR	X23, [SP, #48]

(156) 0x40e040 LDP	X19, X20, [SP, #16]

(156) 0x40e044 LDP	X21, X22, [SP, #32]

(156) 0x40e048 LDP	X29, X30, [SP], #64

(156) 0x40e04c RET

  (153) 0x40e050 MOVZ	W6, #0

  (153) 0x40e054 B	40de6c

0x40e058 ADD	W14, W14, #1

0x40e05c MOVZ	W0, #0

0x40e060 B	40dc84

  (151) 0x40e064 ORR	X1, XZR, X19

  (151) 0x40e068 B	40e020

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.83	2.75	2.83	2.83	3.00	2.75	1.00	1.00	1.00	1.00	2.67	2.67	2.67	2.00	2.00
cycles	2.50	2.50	2.83	2.75	2.83	2.83	3.00	2.75	1.00	1.00	1.00	1.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (2.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40dc40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W14, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W14, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W8, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40e058 <kineticEnergy._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W14, W8, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W17, W14, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40e018 <kineticEnergy._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X23, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SBFM X8, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV V16.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD W14, W14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40dc84 <kineticEnergy._omp_fn.0+0x44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 52% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.83	2.75	2.83	2.83	3.00	2.75	1.00	1.00	1.00	1.00	2.67	2.67	2.67	2.00	2.00
cycles	2.50	2.50	2.83	2.75	2.83	2.83	3.00	2.75	1.00	1.00	1.00	1.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

2% of peak load performance is reached (2.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40dc40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W8, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W14, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W14, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W8, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40e058 <kineticEnergy._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W14, W8, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVI D7, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W17, W14, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40e018 <kineticEnergy._omp_fn.0+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X23, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SBFM X8, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV V16.2D, #0.5000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADD W14, W14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 40dc84 <kineticEnergy._omp_fn.0+0x44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy._omp_fn.0–	0.09	0.01
▼Loop 156 - timestep.c:107-116 - exec–	0.00	0.00
▼Loop 153 - timestep.c:110-116 - exec–	0.00	0.00
▼Loop 152 - timestep.c:110-115 - exec–	0.01	0.01
○Loop 154 - timestep.c:110-115 - exec	0.06	0.01
○Loop 155 - timestep.c:110-116 - exec	0.01	0.00
○Loop 151 - timestep.c:107-107 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code