OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.20% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x40d7e0 STP	X29, X30, [SP, #976]!

0x40d7e4 ADD	X29, SP, #0

0x40d7e8 STP	X19, X20, [SP, #16]

0x40d7ec ORR	X20, XZR, X0

0x40d7f0 STR	X21, [SP, #32]

0x40d7f4 LDR	W21, [X0, #16]

0x40d7f8 BL	402640

0x40d7fc ORR	W19, WZR, W0

0x40d800 BL	402660

0x40d804 ORR	W3, WZR, W0

0x40d808 SDIV	W11, W21, W19

0x40d80c MSUB	W1, W11, W19, W21

0x40d810 CMP	W0, W1

0x40d814 B.LT	40dc30

0x40d818 MADD	W2, W11, W3, W1

0x40d81c ADD	W30, W11, W2

0x40d820 CMP	W2, W30

0x40d824 B.GE	40da68

0x40d828 LDR	X13, [X20]

0x40d82c MOVZ	W0, #1536

0x40d830 SBFM	X10, X2, #0, #31

0x40d834 MOVZ	W15, #24

0x40d838 MOVZ	W14, #48

0x40d83c LDR	D31, [X20, #8]

0x40d840 SMADDL	X3, W2, W0, XZR

0x40d844 LDR	X4, [X13, #24]

0x40d848 DUP	V30.2D, V31.D[0]

0x40d84c LDR	X12, [X4, #120]

    (147) 0x40d850 LDR	W20, [X12, X10,LSL #2]

    (147) 0x40d854 CMP	W20, #0

    (147) 0x40d858 B.LE	40da58

    (147) 0x40d85c LDR	X5, [X13, #32]

    (147) 0x40d860 LDP	X16, X8, [X5, #32]

    (147) 0x40d864 ADD	X18, X16, X3

    (147) 0x40d868 ADD	X6, X8, X3

    (147) 0x40d86c CMP	W20, #1

    (147) 0x40d870 B.EQ	40da78

    (147) 0x40d874 ADD	X7, X3, #48

    (147) 0x40d878 ADD	X6, X8, X3

    (147) 0x40d87c ADD	X9, X16, X7

    (147) 0x40d880 ADD	X17, X8, X7

    (147) 0x40d884 CMP	X6, X9

    (147) 0x40d888 ADD	X18, X16, X3

    (147) 0x40d88c CCMP	X18, X17, #2, #3

    (147) 0x40d890 B.CC	40da78

    (147) 0x40d894 UBFM	W21, W20, #1, #31

    (147) 0x40d898 ORR	X19, XZR, #3841

    (147) 0x40d89c MOVK	X19, #43691

    (147) 0x40d8a0 ORR	X0, XZR, X18

    (147) 0x40d8a4 UMADDL	X11, W21, W14, X18

    (147) 0x40d8a8 MOVK	X19, #2730

    (147) 0x40d8ac ORR	X1, XZR, X6

    (147) 0x40d8b0 SUB	X2, X11, X18

    (147) 0x40d8b4 SUB	X4, X2, #48

    (147) 0x40d8b8 UBFM	X5, X4, #4, #63

    (147) 0x40d8bc MADD	X7, X5, X19, XZR

    (147) 0x40d8c0 ADD	X9, X7, #1

    (147) 0x40d8c4 ANDS	X17, X9, #4160

    (147) 0x40d8c8 B.EQ	40d960

    (147) 0x40d8cc CMP	X17, #1

    (147) 0x40d8d0 B.EQ	40d930

    (147) 0x40d8d4 CMP	X17, #2

    (147) 0x40d8d8 B.EQ	40d908

    (147) 0x40d8dc LDP	Q1, Q0, [X18, #16]

    (147) 0x40d8e0 ADD	X0, X18, #48

    (147) 0x40d8e4 ADD	X1, X6, #48

    (147) 0x40d8e8 LDP	Q3, Q2, [X6, #16]

    (147) 0x40d8ec LDR	Q21, [X8, X3]

    (147) 0x40d8f0 LDR	Q20, [X16, X3]

    (147) 0x40d8f4 FMLA	V1.2D, V30.2D, V3.2D

    (147) 0x40d8f8 FMLA	V20.2D, V30.2D, V21.2D

    (147) 0x40d8fc FMLA	V0.2D, V30.2D, V2.2D

    (147) 0x40d900 STR	Q20, [X16, X3]

    (147) 0x40d904 STP	Q1, Q0, [X18, #16]

    (147) 0x40d908 LDR	Q22, [X1, #32]

    (147) 0x40d90c LDP	Q6, Q19, [X0]

    (147) 0x40d910 ADD	X0, X0, #48

    (147) 0x40d914 LDP	Q7, Q23, [X1], #48

    (147) 0x40d918 LDUR	Q18, [X0, #496]

    (147) 0x40d91c FMLA	V18.2D, V30.2D, V22.2D

    (147) 0x40d920 FMLA	V19.2D, V30.2D, V23.2D

    (147) 0x40d924 FMLA	V6.2D, V30.2D, V7.2D

    (147) 0x40d928 STUR	Q18, [X0, #496]

    (147) 0x40d92c STP	Q6, Q19, [X0, #2000]

    (147) 0x40d930 LDR	Q16, [X1, #32]

    (147) 0x40d934 LDP	Q4, Q25, [X0]

    (147) 0x40d938 ADD	X0, X0, #48

    (147) 0x40d93c LDP	Q5, Q17, [X1], #48

    (147) 0x40d940 LDUR	Q24, [X0, #496]

    (147) 0x40d944 FMLA	V24.2D, V30.2D, V16.2D

    (147) 0x40d948 FMLA	V25.2D, V30.2D, V17.2D

    (147) 0x40d94c FMLA	V4.2D, V30.2D, V5.2D

    (147) 0x40d950 STUR	Q24, [X0, #496]

    (147) 0x40d954 STP	Q4, Q25, [X0, #2000]

    (147) 0x40d958 CMP	X0, X11

    (147) 0x40d95c B.EQ	40da14

      (149) 0x40d960 LDP	Q27, Q26, [X1, #16]

      (149) 0x40d964 ORR	X21, XZR, X1

      (149) 0x40d968 ADD	X19, X0, #48

      (149) 0x40d96c ADD	X6, X0, #96

      (149) 0x40d970 ADD	X18, X1, #96

      (149) 0x40d974 LDP	Q28, Q3, [X0, #32]

      (149) 0x40d978 ADD	X2, X0, #144

      (149) 0x40d97c ADD	X4, X1, #144

      (149) 0x40d980 ADD	X1, X1, #192

      (149) 0x40d984 LDP	Q21, Q29, [X0]

      (149) 0x40d988 ADD	X0, X0, #192

      (149) 0x40d98c LDR	Q20, [X21], #48

      (149) 0x40d990 FMLA	V28.2D, V30.2D, V26.2D

      (149) 0x40d994 FMLA	V29.2D, V30.2D, V27.2D

      (149) 0x40d998 FMLA	V21.2D, V30.2D, V20.2D

      (149) 0x40d99c STUR	Q28, [X0, #352]

      (149) 0x40d9a0 STP	Q21, Q29, [X0, #1856]

      (149) 0x40d9a4 LDP	Q2, Q6, [X19, #16]

      (149) 0x40d9a8 LDP	Q1, Q0, [X21, #16]

      (149) 0x40d9ac LDUR	Q19, [X1, #368]

      (149) 0x40d9b0 FMLA	V3.2D, V30.2D, V19.2D

      (149) 0x40d9b4 FMLA	V2.2D, V30.2D, V1.2D

      (149) 0x40d9b8 FMLA	V6.2D, V30.2D, V0.2D

      (149) 0x40d9bc STUR	Q3, [X0, #368]

      (149) 0x40d9c0 STP	Q2, Q6, [X19, #16]

      (149) 0x40d9c4 LDP	Q22, Q7, [X6, #16]

      (149) 0x40d9c8 LDP	Q23, Q18, [X18, #16]

      (149) 0x40d9cc LDUR	Q25, [X1, #416]

      (149) 0x40d9d0 LDUR	Q4, [X0, #416]

      (149) 0x40d9d4 FMLA	V22.2D, V30.2D, V23.2D

      (149) 0x40d9d8 FMLA	V4.2D, V30.2D, V25.2D

      (149) 0x40d9dc FMLA	V7.2D, V30.2D, V18.2D

      (149) 0x40d9e0 STUR	Q4, [X0, #416]

      (149) 0x40d9e4 STP	Q22, Q7, [X6, #16]

      (149) 0x40d9e8 LDP	Q16, Q5, [X2, #16]

      (149) 0x40d9ec LDP	Q24, Q17, [X4, #16]

      (149) 0x40d9f0 LDUR	Q21, [X0, #464]

      (149) 0x40d9f4 LDUR	Q29, [X1, #464]

      (149) 0x40d9f8 FMLA	V16.2D, V30.2D, V24.2D

      (149) 0x40d9fc FMLA	V21.2D, V30.2D, V29.2D

      (149) 0x40da00 FMLA	V5.2D, V30.2D, V17.2D

      (149) 0x40da04 STUR	Q21, [X0, #464]

      (149) 0x40da08 STP	Q16, Q5, [X2, #16]

      (149) 0x40da0c CMP	X0, X11

      (149) 0x40da10 B.NE	40d960

    (147) 0x40da14 AND	W11, W20, #1951

    (147) 0x40da18 TBZ	W20, #0, 40da58

    (147) 0x40da1c ADD	W20, W11, W10,LSL #6

    (147) 0x40da20 SMADDL	X5, W20, W15, XZR

    (147) 0x40da24 LDR	D27, [X8, X5]

    (147) 0x40da28 ADD	X7, X16, X5

    (147) 0x40da2c ADD	X8, X8, X5

    (147) 0x40da30 LDR	D26, [X16, X5]

    (147) 0x40da34 FMADD	D20, D31, D27, D26

    (147) 0x40da38 STR	D20, [X16, X5]

    (147) 0x40da3c LDR	D2, [X8, #8]

    (147) 0x40da40 LDP	D3, D28, [X7, #8]

    (147) 0x40da44 FMADD	D6, D31, D2, D3

    (147) 0x40da48 STR	D6, [X7, #8]

    (147) 0x40da4c LDR	D1, [X8, #16]

    (147) 0x40da50 FMADD	D0, D31, D1, D28

    (147) 0x40da54 STR	D0, [X7, #16]

    (147) 0x40da58 ADD	X10, X10, #1

    (147) 0x40da5c ADD	X3, X3, #1536

    (147) 0x40da60 CMP	W30, W10

    (147) 0x40da64 B.GT	40d850

(150) 0x40da68 LDR	X21, [SP, #32]

(150) 0x40da6c LDP	X19, X20, [SP, #16]

(150) 0x40da70 LDP	X29, X30, [SP], #48

(150) 0x40da74 RET

  (148) 0x40da78 UMADDL	X17, W20, W15, X18

  (148) 0x40da7c ORR	X16, XZR, #3841

  (148) 0x40da80 ORR	X0, XZR, X18

  (148) 0x40da84 MOVK	X16, #43691

  (148) 0x40da88 ORR	X1, XZR, X6

  (148) 0x40da8c MOVK	X16, #2730

  (148) 0x40da90 SUB	X9, X17, X18

  (148) 0x40da94 SUB	X21, X9, #24

  (148) 0x40da98 UBFM	X19, X21, #3, #63

  (148) 0x40da9c MADD	X2, X19, X16, XZR

  (148) 0x40daa0 ADD	X4, X2, #1

  (148) 0x40daa4 ANDS	X11, X4, #4160

  (148) 0x40daa8 B.EQ	40db60

  (148) 0x40daac CMP	X11, #1

  (148) 0x40dab0 B.EQ	40db24

  (148) 0x40dab4 CMP	X11, #2

  (148) 0x40dab8 B.EQ	40daf0

  (148) 0x40dabc LDR	D23, [X6]

  (148) 0x40dac0 ADD	X0, X18, #24

  (148) 0x40dac4 ADD	X1, X6, #24

  (148) 0x40dac8 LDP	D19, D22, [X18]

  (148) 0x40dacc LDR	D7, [X18, #16]

  (148) 0x40dad0 FMADD	D18, D31, D23, D19

  (148) 0x40dad4 STR	D18, [X18]

  (148) 0x40dad8 LDR	D4, [X6, #8]

  (148) 0x40dadc FMADD	D25, D31, D4, D22

  (148) 0x40dae0 STR	D25, [X18, #8]

  (148) 0x40dae4 LDR	D16, [X6, #16]

  (148) 0x40dae8 FMADD	D5, D31, D16, D7

  (148) 0x40daec STR	D5, [X18, #16]

  (148) 0x40daf0 LDR	D29, [X1]

  (148) 0x40daf4 ADD	X1, X1, #24

  (148) 0x40daf8 LDP	D24, D17, [X0]

  (148) 0x40dafc ADD	X0, X0, #24

  (148) 0x40db00 LDUR	D21, [X0, #504]

  (148) 0x40db04 FMADD	D27, D31, D29, D24

  (148) 0x40db08 STUR	D27, [X0, #488]

  (148) 0x40db0c LDUR	D26, [X1, #496]

  (148) 0x40db10 FMADD	D20, D31, D26, D17

  (148) 0x40db14 STUR	D20, [X0, #496]

  (148) 0x40db18 LDUR	D3, [X1, #504]

  (148) 0x40db1c FMADD	D28, D31, D3, D21

  (148) 0x40db20 STUR	D28, [X0, #504]

  (148) 0x40db24 LDR	D0, [X1]

  (148) 0x40db28 ADD	X1, X1, #24

  (148) 0x40db2c LDP	D2, D6, [X0]

  (148) 0x40db30 ADD	X0, X0, #24

  (148) 0x40db34 LDUR	D1, [X0, #504]

  (148) 0x40db38 FMADD	D19, D31, D0, D2

  (148) 0x40db3c STUR	D19, [X0, #488]

  (148) 0x40db40 LDUR	D22, [X1, #496]

  (148) 0x40db44 FMADD	D7, D31, D22, D6

  (148) 0x40db48 STUR	D7, [X0, #496]

  (148) 0x40db4c LDUR	D23, [X1, #504]

  (148) 0x40db50 FMADD	D18, D31, D23, D1

  (148) 0x40db54 STUR	D18, [X0, #504]

  (148) 0x40db58 CMP	X17, X0

  (148) 0x40db5c B.EQ	40da58

    (146) 0x40db60 LDR	D5, [X1]

    (146) 0x40db64 ADD	X18, X0, #24

    (146) 0x40db68 ADD	X6, X0, #48

    (146) 0x40db6c ADD	X5, X0, #72

    (146) 0x40db70 ORR	X20, XZR, X1

    (146) 0x40db74 LDP	D4, D25, [X0]

    (146) 0x40db78 ADD	X1, X1, #96

    (146) 0x40db7c LDP	D16, D24, [X0, #16]

    (146) 0x40db80 ADD	X0, X0, #96

    (146) 0x40db84 FMADD	D17, D31, D5, D4

    (146) 0x40db88 STUR	D17, [X0, #416]

    (146) 0x40db8c LDUR	D21, [X1, #424]

    (146) 0x40db90 FMADD	D29, D31, D21, D25

    (146) 0x40db94 STUR	D29, [X0, #424]

    (146) 0x40db98 LDUR	D27, [X1, #432]

    (146) 0x40db9c FMADD	D26, D31, D27, D16

    (146) 0x40dba0 STUR	D26, [X0, #432]

    (146) 0x40dba4 LDUR	D20, [X1, #440]

    (146) 0x40dba8 FMADD	D3, D31, D20, D24

    (146) 0x40dbac STUR	D3, [X0, #440]

    (146) 0x40dbb0 LDUR	D6, [X1, #448]

    (146) 0x40dbb4 LDP	D28, D2, [X18, #8]

    (146) 0x40dbb8 FMADD	D1, D31, D6, D28

    (146) 0x40dbbc STR	D1, [X18, #8]

    (146) 0x40dbc0 LDUR	D0, [X1, #456]

    (146) 0x40dbc4 FMADD	D19, D31, D0, D2

    (146) 0x40dbc8 STR	D19, [X18, #16]

    (146) 0x40dbcc LDUR	D7, [X1, #464]

    (146) 0x40dbd0 LDUR	D22, [X0, #464]

    (146) 0x40dbd4 FMADD	D23, D31, D7, D22

    (146) 0x40dbd8 STUR	D23, [X0, #464]

    (146) 0x40dbdc LDUR	D25, [X1, #472]

    (146) 0x40dbe0 LDP	D18, D4, [X6, #8]

    (146) 0x40dbe4 FMADD	D16, D31, D25, D18

    (146) 0x40dbe8 STR	D16, [X6, #8]

    (146) 0x40dbec LDUR	D24, [X1, #480]

    (146) 0x40dbf0 FMADD	D5, D31, D24, D4

    (146) 0x40dbf4 STR	D5, [X6, #16]

    (146) 0x40dbf8 LDUR	D17, [X0, #488]

    (146) 0x40dbfc LDUR	D21, [X1, #488]

    (146) 0x40dc00 FMADD	D29, D31, D21, D17

    (146) 0x40dc04 STUR	D29, [X0, #488]

    (146) 0x40dc08 LDUR	D27, [X1, #496]

    (146) 0x40dc0c LDP	D26, D20, [X5, #8]

    (146) 0x40dc10 FMADD	D3, D31, D27, D26

    (146) 0x40dc14 STR	D3, [X5, #8]

    (146) 0x40dc18 LDR	D28, [X20, #88]

    (146) 0x40dc1c FMADD	D2, D31, D28, D20

    (146) 0x40dc20 STR	D2, [X5, #16]

    (146) 0x40dc24 CMP	X17, X0

    (146) 0x40dc28 B.NE	40db60

  (148) 0x40dc2c B	40da58

0x40dc30 ADD	W11, W11, #1

0x40dc34 MOVZ	W1, #0

0x40dc38 B	40d818

0x40dc3c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.14+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50
cycles	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (2.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W11, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W11, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40dc30 <advanceVelocity._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W11, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40da68 <advanceVelocity._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D31, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SMADDL X3, W2, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X12, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40d818 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50
cycles	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (2.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W11, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W11, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40dc30 <advanceVelocity._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W11, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40da68 <advanceVelocity._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D31, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SMADDL X3, W2, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X12, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40d818 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	2.20	0.18
▼Loop 150 - timestep.c:71-78 - exec–	0.00	0.00
▼Loop 148 - timestep.c:71-78 - exec–	0.00	0.00
▼Loop 147 - timestep.c:74-78 - exec–	0.58	0.03
○Loop 149 - timestep.c:74-76 - exec	1.63	0.10
○Loop 146 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code