OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 1.26% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x40d600 STP	X29, X30, [SP, #976]!

0x40d604 ADD	X29, SP, #0

0x40d608 STP	X19, X20, [SP, #16]

0x40d60c ORR	X20, XZR, X0

0x40d610 STR	X21, [SP, #32]

0x40d614 LDR	W21, [X0, #16]

0x40d618 BL	402640

0x40d61c ORR	W19, WZR, W0

0x40d620 BL	402660

0x40d624 ORR	W9, WZR, W0

0x40d628 SDIV	W13, W21, W19

0x40d62c MSUB	W1, W13, W19, W21

0x40d630 CMP	W0, W1

0x40d634 B.LT	40d7d0

(143) 0x40d638 MADD	W2, W13, W9, W1

(143) 0x40d63c ADD	W16, W13, W2

(143) 0x40d640 CMP	W2, W16

(143) 0x40d644 B.GE	40d7c0

(143) 0x40d648 LDR	X14, [X20]

(143) 0x40d64c MOVZ	W0, #1536

(143) 0x40d650 FMOV	D30, #1.0000000

(143) 0x40d654 SBFM	X12, X2, #0, #31

(143) 0x40d658 SBFM	X11, X2, #58, #31

(143) 0x40d65c LDR	D31, [X20, #8]

(143) 0x40d660 SMADDL	X9, W2, W0, XZR

(143) 0x40d664 LDR	X3, [X14, #24]

(143) 0x40d668 LDR	X15, [X3, #120]

  (144) 0x40d66c LDR	W6, [X15, X12,LSL #2]

  (144) 0x40d670 CMP	W6, #0

  (144) 0x40d674 B.LE	40d7ac

  (144) 0x40d678 LDP	X5, X7, [X14, #32]

  (144) 0x40d67c SBFM	X4, X11, #0, #31

  (144) 0x40d680 ADD	X10, X11, W6,SXTW

  (144) 0x40d684 LDR	X18, [X5, #32]

  (144) 0x40d688 LDP	X8, X17, [X5, #16]

  (144) 0x40d68c ADD	X21, X18, X9

  (144) 0x40d690 ADD	X19, X17, X9

  (144) 0x40d694 TBZ	W6, #0, 40d700

  (144) 0x40d698 LDRSW	X30, [X8, X11,SXTW #2]

  (144) 0x40d69c ADD	X4, X4, #1

  (144) 0x40d6a0 ADD	X21, X21, #24

  (144) 0x40d6a4 LDR	D23, [X18, X9]

  (144) 0x40d6a8 LDR	D22, [X17, X9]

  (144) 0x40d6ac ADD	X20, X7, X30,LSL #4

  (144) 0x40d6b0 LDR	D29, [X20, #8]

  (144) 0x40d6b4 FMUL	D0, D31, D23

  (144) 0x40d6b8 FDIV	D1, D30, D29

  (144) 0x40d6bc FMADD	D2, D1, D0, D22

  (144) 0x40d6c0 STR	D2, [X17, X9]

  (144) 0x40d6c4 LDUR	D21, [X21, #496]

  (144) 0x40d6c8 LDP	D20, D18, [X19, #8]

  (144) 0x40d6cc ADD	X19, X19, #24

  (144) 0x40d6d0 FMUL	D3, D31, D21

  (144) 0x40d6d4 FMADD	D4, D1, D3, D20

  (144) 0x40d6d8 STUR	D4, [X19, #496]

  (144) 0x40d6dc LDUR	D19, [X21, #504]

  (144) 0x40d6e0 FMUL	D5, D31, D19

  (144) 0x40d6e4 FMADD	D6, D1, D5, D18

  (144) 0x40d6e8 STUR	D6, [X19, #504]

  (144) 0x40d6ec CMP	X10, X4

  (144) 0x40d6f0 B.EQ	40d7ac

  (144) 0x40d6f4 HINT	#0

  (144) 0x40d6f8 HINT	#0

  (144) 0x40d6fc HINT	#0

    (145) 0x40d700 LDRSW	X13, [X8, X4,LSL #2]

    (145) 0x40d704 ADD	X1, X4, #1

    (145) 0x40d708 ADD	X2, X19, #24

    (145) 0x40d70c ORR	X0, XZR, X21

    (145) 0x40d710 ADD	X4, X4, #2

    (145) 0x40d714 LDR	D17, [X21]

    (145) 0x40d718 ADD	X21, X21, #48

    (145) 0x40d71c LDP	D16, D24, [X19]

    (145) 0x40d720 ADD	X3, X7, X13,LSL #4

    (145) 0x40d724 LDRSW	X6, [X8, X1,LSL #2]

    (145) 0x40d728 LDR	D26, [X3, #8]

    (145) 0x40d72c FMUL	D7, D31, D17

    (145) 0x40d730 LDP	D25, D27, [X19, #16]

    (145) 0x40d734 ADD	X19, X19, #48

    (145) 0x40d738 ADD	X5, X7, X6,LSL #4

    (145) 0x40d73c FDIV	D28, D30, D26

    (145) 0x40d740 FMADD	D23, D28, D7, D16

    (145) 0x40d744 STUR	D23, [X19, #464]

    (145) 0x40d748 LDUR	D22, [X21, #472]

    (145) 0x40d74c FMUL	D0, D31, D22

    (145) 0x40d750 FMADD	D29, D28, D0, D24

    (145) 0x40d754 STUR	D29, [X19, #472]

    (145) 0x40d758 LDUR	D1, [X21, #480]

    (145) 0x40d75c FMUL	D2, D31, D1

    (145) 0x40d760 FMADD	D20, D28, D2, D25

    (145) 0x40d764 STUR	D20, [X19, #480]

    (145) 0x40d768 LDR	D3, [X5, #8]

    (145) 0x40d76c LDUR	D18, [X21, #488]

    (145) 0x40d770 FDIV	D4, D30, D3

    (145) 0x40d774 FMUL	D21, D31, D18

    (145) 0x40d778 FMADD	D19, D4, D21, D27

    (145) 0x40d77c STUR	D19, [X19, #488]

    (145) 0x40d780 LDUR	D16, [X21, #496]

    (145) 0x40d784 LDP	D5, D6, [X2, #8]

    (145) 0x40d788 FMUL	D24, D31, D16

    (145) 0x40d78c FMADD	D25, D4, D24, D5

    (145) 0x40d790 STR	D25, [X2, #8]

    (145) 0x40d794 LDR	D27, [X0, #40]

    (145) 0x40d798 FMUL	D17, D31, D27

    (145) 0x40d79c FMADD	D7, D4, D17, D6

    (145) 0x40d7a0 STR	D7, [X2, #16]

    (145) 0x40d7a4 CMP	X10, X4

    (145) 0x40d7a8 B.NE	40d700

  (144) 0x40d7ac ADD	X12, X12, #1

  (144) 0x40d7b0 ADD	X9, X9, #1536

  (144) 0x40d7b4 ADD	X11, X11, #64

  (144) 0x40d7b8 CMP	W16, W12

  (144) 0x40d7bc B.GT	40d66c

(143) 0x40d7c0 LDR	X21, [SP, #32]

(143) 0x40d7c4 LDP	X19, X20, [SP, #16]

(143) 0x40d7c8 LDP	X29, X30, [SP], #48

(143) 0x40d7cc RET

(143) 0x40d7d0 ADD	W13, W13, #1

(143) 0x40d7d4 MOVZ	W1, #0

(143) 0x40d7d8 B	40d638

0x40d7dc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.57+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.43+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W13, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W13, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40d7d0 <advancePosition._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d600

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W13, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W13, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40d7d0 <advancePosition._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	1.26	0.10
▼Loop 143 - timestep.c:85-94 - exec–	0.00	0.00
▼Loop 144 - timestep.c:88-94 - exec–	0.12	0.01
○Loop 145 - timestep.c:88-94 - exec	1.15	0.07

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code