OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 90.25% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x40af80 STP	X29, X30, [SP, #944]!

0x40af84 ADD	X29, SP, #0

0x40af88 STP	X19, X20, [SP, #16]

0x40af8c ORR	X19, XZR, X0

0x40af90 STP	X21, X22, [SP, #32]

0x40af94 STP	X23, X24, [SP, #48]

0x40af98 LDR	X20, [X0]

0x40af9c BL	402640

0x40afa0 ORR	W21, WZR, W0

0x40afa4 BL	402660

0x40afa8 ORR	W11, WZR, W0

0x40afac LDR	X23, [X20, #24]

0x40afb0 LDR	W22, [X23, #12]

0x40afb4 SDIV	W15, W22, W21

0x40afb8 MSUB	W0, W15, W21, W22

0x40afbc CMP	W11, W0

0x40afc0 B.LT	40b494

0x40afc4 MADD	W1, W15, W11, W0

0x40afc8 ADD	W15, W15, W1

0x40afcc CMP	W1, W15

0x40afd0 B.GE	40b4ac

(129) 0x40afd4 LDP	D23, D27, [X19, #8]

(129) 0x40afd8 FMOV	D31, #-4.0000000

(129) 0x40afdc ORN	W2, WZR, W1

(129) 0x40afe0 SBFM	X13, X1, #0, #31

(129) 0x40afe4 ADD	W3, W15, W2

(129) 0x40afe8 UBFM	W11, W1, #26, #25

(129) 0x40afec LDR	W5, [X19, #48]

(129) 0x40aff0 AND	W4, W3, #128

(129) 0x40aff4 LDR	X16, [X23, #120]

(129) 0x40aff8 FMUL	D23, D23, D31

(129) 0x40affc LDP	D21, D22, [X19, #24]

(129) 0x40b000 SBFM	X22, X5, #62, #31

(129) 0x40b004 CMP	W5, #0

(129) 0x40b008 B.LE	40b4b4

(129) 0x40b00c STP	X25, X26, [SP, #64]

(129) 0x40b010 MOVI	D26, #0

(129) 0x40b014 FMOV	D24, #1.0000000

(129) 0x40b018 MOVZ	W30, #1536

(129) 0x40b01c FMOV	D25, #0.5000000

(129) 0x40b020 FMOV	D19, #12.0000000

(129) 0x40b024 FMOV	D20, #-6.0000000

(129) 0x40b028 LDR	X23, [X23, #128]

(129) 0x40b02c LDR	W17, [X16, X13,LSL #2]

  (131) 0x40b030 ADD	W12, W17, W11

  (131) 0x40b034 SBFM	X18, X13, #55, #25

  (131) 0x40b038 LDR	X14, [X23, X13,LSL #3]

  (131) 0x40b03c ADD	X21, X22, X14

    (130) 0x40b040 LDR	W9, [X14]

    (130) 0x40b044 TBNZ	W9, #31, 40b590

    (130) 0x40b048 LDR	W24, [X16, X9,UXTW #2]

    (130) 0x40b04c CMP	W17, #0

    (130) 0x40b050 B.LE	40b150

    (130) 0x40b054 ORN	W25, WZR, W11

    (130) 0x40b058 UBFM	W10, W9, #26, #25

    (130) 0x40b05c UMADDL	X9, W9, W30, XZR

    (130) 0x40b060 ADD	W26, W25, W12

    (130) 0x40b064 ADD	W6, W24, W10

    (130) 0x40b068 AND	W0, W26, #128

    (130) 0x40b06c ORR	X5, XZR, X18

    (130) 0x40b070 ORR	W8, WZR, W11

    (130) 0x40b074 CMP	W24, #0

    (130) 0x40b078 B.GT	40b174

    (130) 0x40b07c ADD	W8, W11, #1

    (130) 0x40b080 ADD	X5, X18, #8

    (130) 0x40b084 CMP	W8, W12

    (130) 0x40b088 B.GE	40b150

    (130) 0x40b08c CBZ	W0, 40b138

    (130) 0x40b090 CMP	W0, #1

    (130) 0x40b094 B.EQ	40b120

    (130) 0x40b098 CMP	W0, #2

    (130) 0x40b09c B.EQ	40b110

    (130) 0x40b0a0 CMP	W0, #3

    (130) 0x40b0a4 B.EQ	40b100

    (130) 0x40b0a8 CMP	W0, #4

    (130) 0x40b0ac B.EQ	40b0f0

    (130) 0x40b0b0 CMP	W0, #5

    (130) 0x40b0b4 B.EQ	40b0e0

    (130) 0x40b0b8 CMP	W0, #6

    (130) 0x40b0bc B.EQ	40b0d0

    (130) 0x40b0c0 CMP	W24, #0

    (130) 0x40b0c4 B.GT	40b174

    (130) 0x40b0c8 ADD	W8, W8, #1

    (130) 0x40b0cc ADD	X5, X5, #8

    (130) 0x40b0d0 CMP	W24, #0

    (130) 0x40b0d4 B.GT	40b174

    (130) 0x40b0d8 ADD	W8, W8, #1

    (130) 0x40b0dc ADD	X5, X5, #8

    (130) 0x40b0e0 CMP	W24, #0

    (130) 0x40b0e4 B.GT	40b174

    (130) 0x40b0e8 ADD	W8, W8, #1

    (130) 0x40b0ec ADD	X5, X5, #8

    (130) 0x40b0f0 CMP	W24, #0

    (130) 0x40b0f4 B.GT	40b174

    (130) 0x40b0f8 ADD	W8, W8, #1

    (130) 0x40b0fc ADD	X5, X5, #8

    (130) 0x40b100 CMP	W24, #0

    (130) 0x40b104 B.GT	40b174

    (130) 0x40b108 ADD	W8, W8, #1

    (130) 0x40b10c ADD	X5, X5, #8

    (130) 0x40b110 CMP	W24, #0

    (130) 0x40b114 B.GT	40b174

    (130) 0x40b118 ADD	W8, W8, #1

    (130) 0x40b11c ADD	X5, X5, #8

    (130) 0x40b120 CMP	W24, #0

    (130) 0x40b124 B.GT	40b174

    (130) 0x40b128 ADD	W8, W8, #1

    (130) 0x40b12c ADD	X5, X5, #8

    (130) 0x40b130 CMP	W8, W12

    (130) 0x40b134 B.GE	40b150

      (134) 0x40b138 CMP	W24, #0

      (134) 0x40b13c B.GT	40b174

      (134) 0x40b140 ADD	W8, W8, #8

      (134) 0x40b144 ADD	X5, X5, #64

      (134) 0x40b148 CMP	W8, W12

      (134) 0x40b14c B.LT	40b138

    (130) 0x40b150 ADD	X14, X14, #4

    (130) 0x40b154 CMP	X21, X14

    (130) 0x40b158 B.NE	40b040

  (131) 0x40b15c ADD	X13, X13, #1

  (131) 0x40b160 ADD	W11, W11, #64

  (131) 0x40b164 CMP	W15, W13

  (131) 0x40b168 B.LE	40b450

  (131) 0x40b16c LDR	W17, [X16, X13,LSL #2]

  (131) 0x40b170 B	40b030

    (130) 0x40b174 LDR	X7, [X20, #32]

    (130) 0x40b178 HINT	#0

    (130) 0x40b17c HINT	#0

      (132) 0x40b180 ADD	X4, X5, X5,LSL #1

      (132) 0x40b184 ORN	W1, WZR, W10

      (132) 0x40b188 LDR	X24, [X7, #24]

      (132) 0x40b18c ADD	W2, W1, W6

      (132) 0x40b190 AND	W3, W2, #0

      (132) 0x40b194 ADD	X0, X24, X4

      (132) 0x40b198 ADD	X25, X24, X9

      (132) 0x40b19c LDR	D28, [X24, X4]

      (132) 0x40b1a0 LDP	D29, D30, [X0, #8]

      (132) 0x40b1a4 LDP	D17, D18, [X25, #8]

      (132) 0x40b1a8 LDR	D0, [X24, X9]

      (132) 0x40b1ac FSUB	D1, D29, S17

      (132) 0x40b1b0 FSUB	D4, D30, S18

      (132) 0x40b1b4 FSUB	D2, D28, S0

      (132) 0x40b1b8 FMUL	D3, D1, D1

      (132) 0x40b1bc FMADD	D5, D2, D2, D3

      (132) 0x40b1c0 FMADD	D6, D4, D4, D5

      (132) 0x40b1c4 FCMPE	D6, #0

      (132) 0x40b1c8 FCCMPE	D27, D6, #1, #12

      (132) 0x40b1cc CSINC	W26, WZR, WZR, #11

      (132) 0x40b1d0 CBNZ	W26, 40b390

      (132) 0x40b1d4 ADD	W2, W10, #1

      (132) 0x40b1d8 ADD	X1, X25, #24

      (132) 0x40b1dc CMP	W6, W2

      (132) 0x40b1e0 B.LE	40b31c

      (132) 0x40b1e4 CBZ	W3, 40b284

      (132) 0x40b1e8 LDP	D31, D30, [X0, #8]

      (132) 0x40b1ec LDP	D29, D17, [X1, #8]

      (132) 0x40b1f0 LDR	D0, [X24, X4]

      (132) 0x40b1f4 LDR	D18, [X25, #24]

      (132) 0x40b1f8 FSUB	D3, D31, S29

      (132) 0x40b1fc FSUB	D5, D30, S17

      (132) 0x40b200 FSUB	D6, D0, S18

      (132) 0x40b204 FMUL	D16, D3, D3

      (132) 0x40b208 FMADD	D2, D6, D6, D16

      (132) 0x40b20c FMADD	D7, D5, D5, D2

      (132) 0x40b210 FCMPE	D7, #0

      (132) 0x40b214 FCCMPE	D27, D7, #1, #12

      (132) 0x40b218 CSINC	W3, WZR, WZR, #11

      (132) 0x40b21c CBNZ	W3, 40b3f0

      (132) 0x40b220 ADD	W2, W2, #1

      (132) 0x40b224 ADD	X1, X1, #24

      (132) 0x40b228 CMP	W6, W2

      (132) 0x40b22c B.GT	40b284

      (132) 0x40b230 B	40b31c

        (133) 0x40b234 ADD	X3, X1, #24

        (133) 0x40b238 LDP	D0, D29, [X0]

        (133) 0x40b23c ADD	W2, W2, #1

        (133) 0x40b240 LDP	D31, D17, [X3, #8]

        (133) 0x40b244 LDR	D16, [X1, #24]

        (133) 0x40b248 LDR	D30, [X0, #16]

        (133) 0x40b24c FSUB	D18, D29, S31

        (133) 0x40b250 FSUB	D4, D0, S16

        (133) 0x40b254 FSUB	D1, D30, S17

        (133) 0x40b258 FMUL	D7, D18, D18

        (133) 0x40b25c FMADD	D28, D4, D4, D7

        (133) 0x40b260 FMADD	D3, D1, D1, D28

        (133) 0x40b264 FCMPE	D3, #0

        (133) 0x40b268 FCCMPE	D27, D3, #1, #12

        (133) 0x40b26c CSINC	W1, WZR, WZR, #11

        (133) 0x40b270 CBNZ	W1, 40b330

        (133) 0x40b274 ADD	W2, W2, #1

        (133) 0x40b278 ADD	X1, X3, #24

        (133) 0x40b27c CMP	W6, W2

        (133) 0x40b280 B.LE	40b31c

        (133) 0x40b284 LDP	D0, D29, [X0]

        (133) 0x40b288 LDP	D31, D30, [X1]

        (133) 0x40b28c LDR	D7, [X0, #16]

        (133) 0x40b290 LDR	D18, [X1, #16]

        (133) 0x40b294 FSUB	D2, D29, S30

        (133) 0x40b298 FSUB	D28, D0, S31

        (133) 0x40b29c FSUB	D6, D7, S18

        (133) 0x40b2a0 FMUL	D17, D2, D2

        (133) 0x40b2a4 FMADD	D16, D28, D28, D17

        (133) 0x40b2a8 FMADD	D1, D6, D6, D16

        (133) 0x40b2ac FCMPE	D1, #0

        (133) 0x40b2b0 FCCMPE	D27, D1, #1, #12

        (133) 0x40b2b4 CSINC	W3, WZR, WZR, #11

        (133) 0x40b2b8 CBZ	W3, 40b234

        (133) 0x40b2bc FDIV	D4, D24, D1

        (133) 0x40b2c0 LDP	X24, X25, [X7, #40]

        (133) 0x40b2c4 LDR	D3, [X25, X5]

        (133) 0x40b2c8 ADD	X26, X24, X4

        (133) 0x40b2cc FMUL	D5, D4, D4

        (133) 0x40b2d0 FMUL	D0, D21, D4

        (133) 0x40b2d4 FMUL	D29, D23, D4

        (133) 0x40b2d8 FMUL	D31, D5, D0

        (133) 0x40b2dc FMADD	D30, D31, D19, D20

        (133) 0x40b2e0 FSUB	D17, D31, S24

        (133) 0x40b2e4 FNMSUB	D16, D17, D31, D22

        (133) 0x40b2e8 FMUL	D7, D30, D31

        (133) 0x40b2ec FMADD	D18, D16, D25, D3

        (133) 0x40b2f0 FMADD	D26, D16, D25, D26

        (133) 0x40b2f4 FMUL	D1, D7, D29

        (133) 0x40b2f8 STR	D18, [X25, X5]

        (133) 0x40b2fc LDR	D4, [X24, X4]

        (133) 0x40b300 FMSUB	D28, D1, D28, D4

        (133) 0x40b304 STR	D28, [X24, X4]

        (133) 0x40b308 LDP	D3, D5, [X26, #8]

        (133) 0x40b30c FMSUB	D2, D1, D2, D3

        (133) 0x40b310 FMSUB	D6, D1, D6, D5

        (133) 0x40b314 STP	D2, D6, [X26, #8]

        (133) 0x40b318 B	40b234

      (132) 0x40b31c ADD	W8, W8, #1

      (132) 0x40b320 ADD	X5, X5, #8

      (132) 0x40b324 CMP	W12, W8

      (132) 0x40b328 B.GT	40b180

    (130) 0x40b32c B	40b150

        (133) 0x40b330 FDIV	D5, D24, D3

        (133) 0x40b334 LDP	X24, X25, [X7, #40]

        (133) 0x40b338 LDR	D2, [X25, X5]

        (133) 0x40b33c ADD	X26, X24, X4

        (133) 0x40b340 FMUL	D6, D5, D5

        (133) 0x40b344 FMUL	D0, D21, D5

        (133) 0x40b348 FMUL	D29, D23, D5

        (133) 0x40b34c FMUL	D31, D6, D0

        (133) 0x40b350 FMADD	D17, D31, D19, D20

        (133) 0x40b354 FSUB	D30, D31, S24

        (133) 0x40b358 FNMSUB	D16, D30, D31, D22

        (133) 0x40b35c FMUL	D7, D17, D31

        (133) 0x40b360 FMADD	D28, D16, D25, D2

        (133) 0x40b364 FMADD	D26, D16, D25, D26

        (133) 0x40b368 FMUL	D3, D7, D29

        (133) 0x40b36c STR	D28, [X25, X5]

        (133) 0x40b370 LDR	D5, [X24, X4]

        (133) 0x40b374 FMSUB	D4, D3, D4, D5

        (133) 0x40b378 STR	D4, [X24, X4]

        (133) 0x40b37c LDP	D2, D6, [X26, #8]

        (133) 0x40b380 FMSUB	D18, D3, D18, D2

        (133) 0x40b384 FMSUB	D1, D3, D1, D6

        (133) 0x40b388 STP	D18, D1, [X26, #8]

        (133) 0x40b38c B	40b274

      (132) 0x40b390 FDIV	D16, D24, D6

      (132) 0x40b394 LDP	X2, X26, [X7, #40]

      (132) 0x40b398 LDR	D7, [X26, X5]

      (132) 0x40b39c ADD	X1, X2, X4

      (132) 0x40b3a0 FMUL	D28, D16, D16

      (132) 0x40b3a4 FMUL	D0, D21, D16

      (132) 0x40b3a8 FMUL	D31, D23, D16

      (132) 0x40b3ac FMUL	D29, D28, D0

      (132) 0x40b3b0 FMADD	D30, D29, D19, D20

      (132) 0x40b3b4 FSUB	D17, D29, S24

      (132) 0x40b3b8 FNMSUB	D3, D17, D29, D22

      (132) 0x40b3bc FMUL	D18, D30, D29

      (132) 0x40b3c0 FMADD	D5, D3, D25, D7

      (132) 0x40b3c4 FMADD	D26, D3, D25, D26

      (132) 0x40b3c8 FMUL	D6, D18, D31

      (132) 0x40b3cc STR	D5, [X26, X5]

      (132) 0x40b3d0 LDR	D16, [X2, X4]

      (132) 0x40b3d4 FMSUB	D2, D6, D2, D16

      (132) 0x40b3d8 STR	D2, [X2, X4]

      (132) 0x40b3dc LDP	D7, D28, [X1, #8]

      (132) 0x40b3e0 FMSUB	D1, D6, D1, D7

      (132) 0x40b3e4 FMSUB	D4, D6, D4, D28

      (132) 0x40b3e8 STP	D1, D4, [X1, #8]

      (132) 0x40b3ec B	40b1d4

      (132) 0x40b3f0 FDIV	D28, D24, D7

      (132) 0x40b3f4 LDP	X24, X25, [X7, #40]

      (132) 0x40b3f8 LDR	D1, [X25, X5]

      (132) 0x40b3fc ADD	X26, X24, X4

      (132) 0x40b400 FMUL	D4, D28, D28

      (132) 0x40b404 FMUL	D0, D21, D28

      (132) 0x40b408 FMUL	D31, D23, D28

      (132) 0x40b40c FMUL	D30, D4, D0

      (132) 0x40b410 FMADD	D29, D30, D19, D20

      (132) 0x40b414 FSUB	D17, D30, S24

      (132) 0x40b418 FNMSUB	D16, D17, D30, D22

      (132) 0x40b41c FMUL	D18, D29, D30

      (132) 0x40b420 FMADD	D2, D16, D25, D1

      (132) 0x40b424 FMADD	D26, D16, D25, D26

      (132) 0x40b428 FMUL	D7, D18, D31

      (132) 0x40b42c STR	D2, [X25, X5]

      (132) 0x40b430 LDR	D28, [X24, X4]

      (132) 0x40b434 FMSUB	D6, D7, D6, D28

      (132) 0x40b438 STR	D6, [X24, X4]

      (132) 0x40b43c LDP	D1, D4, [X26, #8]

      (132) 0x40b440 FMSUB	D3, D7, D3, D1

      (132) 0x40b444 FMSUB	D5, D7, D5, D4

      (132) 0x40b448 STP	D3, D5, [X26, #8]

      (132) 0x40b44c B	40b220

(129) 0x40b450 LDP	X25, X26, [SP, #64]

(129) 0x40b454 ADD	X13, X19, #40

(129) 0x40b458 LDR	X4, [X13]

  (128) 0x40b45c ORR	X11, XZR, X4

  (128) 0x40b460 FMOV	D0, X4

  (128) 0x40b464 FADD	D29, D26, D0

  (128) 0x40b468 FMOV	X8, D29

  (128) 0x40b46c CAS	X11, X8, [X13]

  (128) 0x40b470 ORR	X5, XZR, X4

  (128) 0x40b474 ORR	X4, XZR, X11

  (128) 0x40b478 CMP	X5, X11

  (128) 0x40b47c B.NE	40b45c

(129) 0x40b480 LDP	X19, X20, [SP, #16]

(129) 0x40b484 LDP	X21, X22, [SP, #32]

(129) 0x40b488 LDP	X23, X24, [SP, #48]

(129) 0x40b48c LDP	X29, X30, [SP], #80

(129) 0x40b490 RET

(129) 0x40b494 ADD	W15, W15, #1

(129) 0x40b498 MOVZ	W0, #0

(129) 0x40b49c MADD	W1, W15, W11, W0

(129) 0x40b4a0 ADD	W15, W15, W1

(129) 0x40b4a4 CMP	W1, W15

(129) 0x40b4a8 B.LT	40afd4

(129) 0x40b4ac MOVI	D26, #0

(129) 0x40b4b0 B	40b454

(129) 0x40b4b4 ADD	X13, X13, #1

(129) 0x40b4b8 ADD	W11, W11, #64

(129) 0x40b4bc CMP	W15, W13

(129) 0x40b4c0 B.LE	40b4ac

(129) 0x40b4c4 CBZ	W4, 40b570

(129) 0x40b4c8 CMP	W4, #1

(129) 0x40b4cc B.EQ	40b558

(129) 0x40b4d0 CMP	W4, #2

(129) 0x40b4d4 B.EQ	40b548

(129) 0x40b4d8 CMP	W4, #3

(129) 0x40b4dc B.EQ	40b538

(129) 0x40b4e0 CMP	W4, #4

(129) 0x40b4e4 B.EQ	40b528

(129) 0x40b4e8 CMP	W4, #5

(129) 0x40b4ec B.EQ	40b518

(129) 0x40b4f0 CMP	W4, #6

(129) 0x40b4f4 B.EQ	40b508

(129) 0x40b4f8 CMP	W5, #0

(129) 0x40b4fc B.GT	40b00c

(129) 0x40b500 ADD	X13, X13, #1

(129) 0x40b504 ADD	W11, W11, #64

(129) 0x40b508 CMP	W5, #0

(129) 0x40b50c B.GT	40b00c

(129) 0x40b510 ADD	X13, X13, #1

(129) 0x40b514 ADD	W11, W11, #64

(129) 0x40b518 CMP	W5, #0

(129) 0x40b51c B.GT	40b00c

(129) 0x40b520 ADD	X13, X13, #1

(129) 0x40b524 ADD	W11, W11, #64

(129) 0x40b528 CMP	W5, #0

(129) 0x40b52c B.GT	40b00c

(129) 0x40b530 ADD	X13, X13, #1

(129) 0x40b534 ADD	W11, W11, #64

(129) 0x40b538 CMP	W5, #0

(129) 0x40b53c B.GT	40b00c

(129) 0x40b540 ADD	X13, X13, #1

(129) 0x40b544 ADD	W11, W11, #64

(129) 0x40b548 CMP	W5, #0

(129) 0x40b54c B.GT	40b00c

(129) 0x40b550 ADD	X13, X13, #1

(129) 0x40b554 ADD	W11, W11, #64

(129) 0x40b558 CMP	W5, #0

(129) 0x40b55c B.GT	40b00c

(129) 0x40b560 ADD	X13, X13, #1

(129) 0x40b564 ADD	W11, W11, #64

(129) 0x40b568 CMP	W15, W13

(129) 0x40b56c B.LE	40b4ac

  (135) 0x40b570 CMP	W5, #0

  (135) 0x40b574 B.GT	40b00c

  (135) 0x40b578 ADD	X13, X13, #8

  (135) 0x40b57c ADD	W11, W11, #512

  (135) 0x40b580 CMP	W15, W13

  (135) 0x40b584 B.GT	40b570

(129) 0x40b588 MOVI	D26, #0

(129) 0x40b58c B	40b454

0x40b590 ADRP	X6,

0x40b594 ADRP	X7,

0x40b598 ADRP	X8,

0x40b59c ADD	X3, X6, #1408

0x40b5a0 ADD	X1, X7, #1576

0x40b5a4 ADD	X0, X8, #1672

0x40b5a8 MOVZ	W2, #182

0x40b5ac BL	402700

Coverage (%)	Name	Source Location	Module
►99.07+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.50 cycles (8.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.58	3.42	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	2.50	2.50	3.58	3.42	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40af80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W11, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X23, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W15, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W15, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W11, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b494 <ljForce._omp_fn.1+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W15, W11, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W15, W15, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b4ac <ljForce._omp_fn.1+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X6, <410590>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X7, <40f594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X8, <40f598>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, #1408	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X7, #1576	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X8, #1672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #182	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402700 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.50 cycles (8.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.58	3.42	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	2.50	2.50	3.58	3.42	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40af80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W11, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X23, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W15, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W15, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W11, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b494 <ljForce._omp_fn.1+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W15, W11, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W15, W15, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b4ac <ljForce._omp_fn.1+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X6, <410590>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X7, <40f594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X8, <40f598>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X6, #1408	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X7, #1576	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X8, #1672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #182	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402700 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	90.25	7.25
▼Loop 129 - ljForce.c:172-216 - exec–	0.00	0.00
▼Loop 131 - ljForce.c:175-216 - exec–	0.01	0.00
▼Loop 130 - ljForce.c:178-216 - exec–	0.22	0.01
▼Loop 132 - ljForce.c:178-216 - exec–	11.69	0.71
○Loop 133 - ljForce.c:191-216 - exec	78.33	4.73
○Loop 134 - ljForce.c:187-191 - exec	0.00	0.00
○Loop 128 - ljForce.c:172-172 - exec	0.00	0.00
○Loop 135 - ljForce.c:178-178 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code