OV - exec - Function computeVcm._omp

	Function: computeVcm._omp_fn.0	Module: exec	Source: initAtoms.c:218-228 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 218 - 228

--------------------------------------------------------------------------------

218:    #pragma omp parallel for reduction(+:v0) reduction(+:v1) reduction(+:v2) reduction(+:v3)

219:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

220:    {

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

[...]

227:          int iSpecies = s->atoms->iSpecies[iOff];

228:          v3 += s->species[iSpecies].mass;

0x408624 STP	X29, X30, [SP, #928]!

0x408628 ADD	X29, SP, #0

0x40862c STP	X19, X20, [SP, #16]

0x408630 ORR	X20, XZR, X0

0x408634 STP	X21, X22, [SP, #32]

0x408638 LDR	X19, [X0]

0x40863c STR	X23, [SP, #48]

0x408640 BL	402640

0x408644 ORR	W21, WZR, W0

0x408648 BL	402660

0x40864c LDR	X23, [X19, #24]

0x408650 ORR	W11, WZR, W0

0x408654 LDR	W22, [X23, #12]

0x408658 SDIV	W14, W22, W21

0x40865c MSUB	W0, W14, W21, W22

0x408660 CMP	W11, W0

0x408664 B.LT	408854

0x408668 MOVI	V29.2D, #0

0x40866c MADD	W1, W14, W11, W0

0x408670 ADD	W16, W14, W1

0x408674 ORR	V28.16B, V29.16B, V29.16B

0x408678 CMP	W1, W16

0x40867c B.GE	40881c

0x408680 LDR	X15, [X23, #120]

0x408684 SBFM	X12, X1, #0, #31

0x408688 SBFM	X11, X1, #58, #31

(88) 0x40868c LDR	W2, [X15, X12,LSL #2]

(88) 0x408690 CMP	W2, #0

(88) 0x408694 B.LE	40880c

(88) 0x408698 LDP	X7, X4, [X19, #32]

(88) 0x40869c ADD	X3, X12, X12,LSL #1

(88) 0x4086a0 ANDS	X6, X2, #4160

(88) 0x4086a4 SBFM	X22, X11, #0, #31

(88) 0x4086a8 ADD	X10, X11, W2,SXTW

(88) 0x4086ac UBFM	X8, X3, #55, #54

(88) 0x4086b0 LDR	X9, [X7, #32]

(88) 0x4086b4 LDR	X5, [X7, #16]

(88) 0x4086b8 ADD	X18, X9, X8

(88) 0x4086bc B.EQ	408754

(88) 0x4086c0 CMP	X6, #1

(88) 0x4086c4 B.EQ	408724

(88) 0x4086c8 CMP	X6, #2

(88) 0x4086cc B.EQ	4086fc

(88) 0x4086d0 LDRSW	X13, [X5, X11,SXTW #2]

(88) 0x4086d4 ADD	X22, X22, #1

(88) 0x4086d8 LDR	D26, [X9, X8]

(88) 0x4086dc LDP	D30, D27, [X18, #8]

(88) 0x4086e0 ADD	X18, X18, #24

(88) 0x4086e4 ADD	X17, X4, X13,LSL #4

(88) 0x4086e8 LDR	D31, [X17, #8]

(88) 0x4086ec MOV	V30.D[1], V26.D[0]

(88) 0x4086f0 MOV	V31.D[1], V27.D[0]

(88) 0x4086f4 FADD	V29.2D, V29.2D, V30.2D

(88) 0x4086f8 FADD	V28.2D, V28.2D, V31.2D

(88) 0x4086fc LDRSW	X30, [X5, X22,LSL #2]

(88) 0x408700 ADD	X22, X22, #1

(88) 0x408704 LDR	D1, [X18, #16]

(88) 0x408708 LDP	D2, D3, [X18], #24

(88) 0x40870c ADD	X21, X4, X30,LSL #4

(88) 0x408710 LDR	D0, [X21, #8]

(88) 0x408714 MOV	V3.D[1], V2.D[0]

(88) 0x408718 MOV	V0.D[1], V1.D[0]

(88) 0x40871c FADD	V29.2D, V29.2D, V3.2D

(88) 0x408720 FADD	V28.2D, V28.2D, V0.2D

(88) 0x408724 LDRSW	X23, [X5, X22,LSL #2]

(88) 0x408728 ADD	X22, X22, #1

(88) 0x40872c LDR	D5, [X18, #16]

(88) 0x408730 LDP	D6, D7, [X18], #24

(88) 0x408734 ADD	X14, X4, X23,LSL #4

(88) 0x408738 LDR	D4, [X14, #8]

(88) 0x40873c MOV	V7.D[1], V6.D[0]

(88) 0x408740 MOV	V4.D[1], V5.D[0]

(88) 0x408744 FADD	V29.2D, V29.2D, V7.2D

(88) 0x408748 FADD	V28.2D, V28.2D, V4.2D

(88) 0x40874c CMP	X10, X22

(88) 0x408750 B.EQ	40880c

  (89) 0x408754 LDRSW	X1, [X5, X22,LSL #2]

  (89) 0x408758 ORR	X3, XZR, X18

  (89) 0x40875c ADD	X2, X22, #1

  (89) 0x408760 ADD	X0, X22, #2

  (89) 0x408764 ADD	X9, X18, #48

  (89) 0x408768 LDR	D18, [X3], #24

  (89) 0x40876c ADD	X13, X22, #3

  (89) 0x408770 ADD	X8, X18, #72

  (89) 0x408774 ADD	X22, X22, #4

  (89) 0x408778 LDP	D16, D17, [X18, #8]

  (89) 0x40877c ADD	X6, X4, X1,LSL #4

  (89) 0x408780 ADD	X1, X18, #24

  (89) 0x408784 ADD	X18, X18, #96

  (89) 0x408788 LDRSW	X7, [X5, X2,LSL #2]

  (89) 0x40878c LDR	D22, [X6, #8]

  (89) 0x408790 LDP	D19, D24, [X3, #8]

  (89) 0x408794 MOV	V16.D[1], V18.D[0]

  (89) 0x408798 ADD	X17, X4, X7,LSL #4

  (89) 0x40879c LDRSW	X23, [X5, X0,LSL #2]

  (89) 0x4087a0 MOV	V22.D[1], V17.D[0]

  (89) 0x4087a4 LDP	D27, D25, [X9, #8]

  (89) 0x4087a8 FADD	V20.2D, V29.2D, V16.2D

  (89) 0x4087ac FMOV	D21, D19

  (89) 0x4087b0 LDRSW	X30, [X5, X13,LSL #2]

  (89) 0x4087b4 ADD	X14, X4, X23,LSL #4

  (89) 0x4087b8 FADD	V23.2D, V28.2D, V22.2D

  (89) 0x4087bc LDR	D28, [X17, #8]

  (89) 0x4087c0 LD1	{V21.D[1]}, [X1]

  (89) 0x4087c4 ADD	X21, X4, X30,LSL #4

  (89) 0x4087c8 LDR	D26, [X14, #8]

  (89) 0x4087cc MOV	V28.D[1], V24.D[0]

  (89) 0x4087d0 LD1	{V27.D[1]}, [X9]

  (89) 0x4087d4 LDUR	D4, [X18, #488]

  (89) 0x4087d8 FADD	V30.2D, V23.2D, V28.2D

  (89) 0x4087dc LDR	D5, [X21, #8]

  (89) 0x4087e0 FADD	V31.2D, V20.2D, V21.2D

  (89) 0x4087e4 LDP	D0, D1, [X8, #8]

  (89) 0x4087e8 MOV	V26.D[1], V25.D[0]

  (89) 0x4087ec FADD	V2.2D, V30.2D, V26.2D

  (89) 0x4087f0 FADD	V3.2D, V31.2D, V27.2D

  (89) 0x4087f4 MOV	V0.D[1], V4.D[0]

  (89) 0x4087f8 MOV	V5.D[1], V1.D[0]

  (89) 0x4087fc FADD	V28.2D, V2.2D, V5.2D

  (89) 0x408800 FADD	V29.2D, V3.2D, V0.2D

  (89) 0x408804 CMP	X10, X22

  (89) 0x408808 B.NE	408754

(88) 0x40880c ADD	X12, X12, #1

(88) 0x408810 ADD	X11, X11, #64

(88) 0x408814 CMP	W16, W12

(88) 0x408818 B.GT	40868c

0x40881c STP	Q28, Q29, [SP, #64]

0x408820 BL	4027d0

0x408824 LDP	Q16, Q29, [SP, #64]

0x408828 LDUR	Q6, [X20, #8]

0x40882c LDUR	Q7, [X20, #24]

0x408830 LDR	X23, [SP, #48]

0x408834 FADD	V17.2D, V6.2D, V16.2D

0x408838 FADD	V18.2D, V7.2D, V29.2D

0x40883c STUR	Q17, [X20, #8]

0x408840 STUR	Q18, [X20, #24]

0x408844 LDP	X19, X20, [SP, #16]

0x408848 LDP	X21, X22, [SP, #32]

0x40884c LDP	X29, X30, [SP], #96

0x408850 B	402590

0x408854 ADD	W14, W14, #1

0x408858 MOVZ	W0, #0

0x40885c B	408668

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-221,227-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 73% of vector register length is used (average across all VPU instructions).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.50 cycles (8.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 148 bytes. The binary function is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.08	2.92	3.00	3.00	3.00	3.00	1.75	1.75	1.75	1.75	6.17	5.83	6.00	2.00	2.00
cycles	3.50	3.50	3.08	2.92	3.00	3.00	3.00	3.00	1.75	1.75	1.75	1.75	6.17	5.83	6.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.38
Overall L1	6.17-12.50

Vectorization ratios

INT

all	28%
load	42%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	42%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

12% of peak load performance is reached (11.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408624

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W11, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W14, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W14, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W11, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 408854 <computeVcm._omp_fn.0+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V29.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MADD W1, W14, W11, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W14, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR V28.16B, V29.16B, V29.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP W1, W16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40881c <computeVcm._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X23, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X12, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X11, X1, #58, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP Q28, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
BL 4027d0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q16, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDUR Q6, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDUR Q7, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD V17.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V18.2D, V7.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STUR Q17, [X20, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q18, [X20, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 402590 <@plt_start@+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 408668 <computeVcm._omp_fn.0+0x44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-221,227-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 73% of vector register length is used (average across all VPU instructions).

Details

33% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
42% of VPU stores are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
12% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.50 cycles (8.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 148 bytes. The binary function is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	3.08	2.92	3.00	3.00	3.00	3.00	1.75	1.75	1.75	1.75	6.17	5.83	6.00	2.00	2.00
cycles	3.50	3.50	3.08	2.92	3.00	3.00	3.00	3.00	1.75	1.75	1.75	1.75	6.17	5.83	6.00	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	5.38
Overall L1	6.17-12.50

Vectorization ratios

INT

all	28%
load	42%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	12%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	42%
store	42%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

12% of peak load performance is reached (11.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408624

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 402640 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402660 <@plt_start@+0x120>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W11, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W14, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W14, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W11, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 408854 <computeVcm._omp_fn.0+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V29.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MADD W1, W14, W11, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W14, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR V28.16B, V29.16B, V29.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
CMP W1, W16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40881c <computeVcm._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X23, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X12, X1, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X11, X1, #58, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP Q28, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
BL 4027d0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q16, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDUR Q6, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDUR Q7, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD V17.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FADD V18.2D, V7.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STUR Q17, [X20, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR Q18, [X20, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 402590 <@plt_start@+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 408668 <computeVcm._omp_fn.0+0x44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼computeVcm._omp_fn.0–	0.01	0.00
▼Loop 88 - initAtoms.c:221-228 - exec–	0.00	0.00
○Loop 89 - initAtoms.c:221-228 - exec	0.01	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code