OV - exec - Function loadAtomsBuffer

	Function: loadAtomsBuffer	Module: exec	Source: haloExchange.c:367-394	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 367 - 394

--------------------------------------------------------------------------------

367:    real_t* pbcFactor = parms->pbcFactor[face];

368:    real3 shift;

369:    shift[0] = pbcFactor[0] * s->domain->globalExtent[0];

370:    shift[1] = pbcFactor[1] * s->domain->globalExtent[1];

371:    shift[2] = pbcFactor[2] * s->domain->globalExtent[2];

372:

373:    int nCells = parms->nCells[face];

374:    int* cellList = parms->cellList[face];

375:    int nBuf = 0;

376:    for (int iCell=0; iCell<nCells; ++iCell)

377:    {

378:       int iBox = cellList[iCell];

379:       int iOff = iBox*MAXATOMS;

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

390:          ++nBuf;

391:       }

392:    }

393:    return nBuf*sizeof(AtomMsg);

394: }

0x406380 LDR	X4, [X1, #16]

0x406384 ADD	X6, X0, W2,SXTW #3

0x406388 LDR	X5, [X6, #72]

0x40638c LDR	W14, [X0, X2,SXTW #2]

0x406390 LDR	D29, [X4, #88]

0x406394 LDR	D2, [X5, #16]

0x406398 LDP	D30, D28, [X4, #72]

0x40639c LDP	D4, D3, [X5]

0x4063a0 LDR	X12, [X6, #24]

0x4063a4 FMUL	D7, D2, D29

0x4063a8 FMUL	D5, D4, D30

0x4063ac FMUL	D6, D3, D28

0x4063b0 CMP	W14, #0

0x4063b4 B.LE	406494

0x4063b8 LDR	X0, [X1, #24]

0x4063bc MOVZ	W7, #0

0x4063c0 MOVZ	W16, #56

0x4063c4 ADD	X17, X12, W14,UXTW #2

0x4063c8 MOVZ	W15, #1536

0x4063cc LDR	X13, [X0, #120]

(46) 0x4063d0 LDR	W10, [X12]

(46) 0x4063d4 SBFM	X8, X10, #62, #31

(46) 0x4063d8 UBFM	W9, W10, #26, #25

(46) 0x4063dc LDR	W2, [X13, X8]

(46) 0x4063e0 ADD	X18, X13, X8

(46) 0x4063e4 CMP	W2, #0

(46) 0x4063e8 B.LE	40647c

(46) 0x4063ec LDR	X11, [X1, #32]

(46) 0x4063f0 SMADDL	X6, W10, W15, XZR

(46) 0x4063f4 SBFM	X5, X9, #0, #31

(46) 0x4063f8 UMADDL	X0, W7, W16, X3

(46) 0x4063fc LDP	X14, X8, [X11, #24]

(46) 0x406400 LDP	X10, X11, [X11, #8]

(46) 0x406404 ADD	X4, X14, X6

(46) 0x406408 ADD	X2, X8, X6

  (47) 0x40640c ADD	W7, W7, #1

  (47) 0x406410 ADD	X4, X4, #24

  (47) 0x406414 LDUR	D1, [X4, #488]

  (47) 0x406418 ADD	X2, X2, #24

  (47) 0x40641c ADD	X0, X0, #56

  (47) 0x406420 LDR	W6, [X10, X5,LSL #2]

  (47) 0x406424 FADD	D0, D1, D5

  (47) 0x406428 STUR	W6, [X0, #456]

  (47) 0x40642c LDR	W14, [X11, X5,LSL #2]

  (47) 0x406430 ADD	X5, X5, #1

  (47) 0x406434 STUR	D0, [X0, #464]

  (47) 0x406438 LDUR	D16, [X4, #496]

  (47) 0x40643c STUR	W14, [X0, #460]

  (47) 0x406440 LDR	W8, [X18]

  (47) 0x406444 FADD	D17, D16, D6

  (47) 0x406448 ADD	W6, W9, W8

  (47) 0x40644c STUR	D17, [X0, #472]

  (47) 0x406450 LDUR	D31, [X4, #504]

  (47) 0x406454 FADD	D18, D31, D7

  (47) 0x406458 STUR	D18, [X0, #480]

  (47) 0x40645c LDUR	D19, [X2, #488]

  (47) 0x406460 STUR	D19, [X0, #488]

  (47) 0x406464 LDUR	D20, [X2, #496]

  (47) 0x406468 STUR	D20, [X0, #496]

  (47) 0x40646c LDUR	D21, [X2, #504]

  (47) 0x406470 STUR	D21, [X0, #504]

  (47) 0x406474 CMP	W6, W5

  (47) 0x406478 B.GT	40640c

(46) 0x40647c ADD	X12, X12, #4

(46) 0x406480 CMP	X17, X12

(46) 0x406484 B.NE	4063d0

0x406488 MOVZ	W1, #56

0x40648c MADD	W0, W7, W1, WZR

0x406490 RET

0x406494 MOVZ	W0, #0

0x406498 RET

0x40649c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	haloExchange.c:367-394
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:367-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.33 to 2.83 cycles (1.18x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00
cycles	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Overall L1	3.33

Vectorization ratios

INT

all	22%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

28% of peak load performance is reached (27.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X0, W2,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X5, [X6, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X0, X2,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X4, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D30, D28, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X12, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D7, D2, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMUL D5, D4, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMUL D6, D3, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
CMP W14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 406494 <loadAtomsBuffer+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W16, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X17, X12, W14,UXTW #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ W15, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X13, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W0, W7, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_1

Source file and lines	haloExchange.c:367-394
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:367-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

40% of VPU loads are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00
cycles	1.50	1.50	1.50	1.50	1.50	1.50	1.50	1.50	0.75	0.75	0.75	0.75	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Overall L1	3.33

Vectorization ratios

INT

all	22%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

28% of peak load performance is reached (27.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X4, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X0, W2,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X5, [X6, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W14, [X0, X2,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D29, [X4, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D2, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D30, D28, [X4, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X12, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D7, D2, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMUL D5, D4, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FMUL D6, D3, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
CMP W14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 406494 <loadAtomsBuffer+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W16, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X17, X12, W14,UXTW #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ W15, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X13, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD W0, W7, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼loadAtomsBuffer–	0.05	0.00
▼Loop 46 - haloExchange.c:376-390 - exec–	0.00	0.02
○Loop 47 - haloExchange.c:380-390 - exec	0.04	0.25

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Cycles and memory resources usage

ASM code