OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.82% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x40a2b0 SUB	SP, SP, #80

0x40a2b4 STP	X29, X30, [SP, #32]

0x40a2b8 STP	X22, X21, [SP, #48]

0x40a2bc STP	X20, X19, [SP, #64]

0x40a2c0 ADD	X29, SP, #32

0x40a2c4 LDR	W8, [X2]

0x40a2c8 SUBS	W22, W8, #1

0x40a2cc B.LT	40a340

0x40a2d0 LDR	W20, [X0]

0x40a2d4 ORR	X19, XZR, X4

0x40a2d8 ORR	X21, XZR, X3

0x40a2dc MOVZ	W8, #1

0x40a2e0 ADRP	X0,

0x40a2e4 ADD	X0, X0, #3032

0x40a2e8 ADD	X3, SP, #16

0x40a2ec SUB	X4, X29, #4

0x40a2f0 SUB	X5, X29, #8

0x40a2f4 STP	W22, WZR, [X29, #504]

0x40a2f8 STR	WZR, [SP, #16]

0x40a2fc STUR	W8, [X29, #500]

0x40a300 SUB	X6, X29, #12

0x40a304 MOVZ	W2, #34

0x40a308 MOVZ	W7, #1

0x40a30c STR	W8, [SP]

0x40a310 ORR	W1, WZR, W20

0x40a314 BL	4023c0

0x40a318 LDP	W9, W8, [X29, #504]

0x40a31c SBFM	X8, X8, #0, #31

0x40a320 CMP	W9, W22

0x40a324 CSEL	W11, W9, W22, #11

0x40a328 CMP	W8, W11

0x40a32c B.LE	40a354

(114) 0x40a330 ADRP	X0,

(114) 0x40a334 ADD	X0, X0, #3056

(114) 0x40a338 ORR	W1, WZR, W20

(114) 0x40a33c BL	402450

(114) 0x40a340 LDP	X20, X19, [SP, #64]

(114) 0x40a344 LDP	X22, X21, [SP, #48]

(114) 0x40a348 LDP	X29, X30, [SP, #32]

(114) 0x40a34c ADD	SP, SP, #80

(114) 0x40a350 RET

(114) 0x40a354 LDR	X9, [X21]

(114) 0x40a358 UBFM	W18, W8, #26, #25

(114) 0x40a35c ADD	W11, W11, #1

(114) 0x40a360 ADD	X12, X19, #8

(114) 0x40a364 LDR	X10, [X9, #24]

(114) 0x40a368 LDR	X10, [X10, #120]

(114) 0x40a36c B	40a390

0x40a370 HINT	#0

0x40a374 HINT	#0

0x40a378 HINT	#0

0x40a37c HINT	#0

(114) 0x40a380 ADD	X8, X8, #1

(114) 0x40a384 ADD	W18, W13, #64

(114) 0x40a388 CMP	W11, W8

(114) 0x40a38c B.EQ	40a330

(114) 0x40a390 LDR	W14, [X10, X8,LSL #2]

(114) 0x40a394 SBFM	X13, X18, #0, #31

(114) 0x40a398 CMP	W14, #1

(114) 0x40a39c B.LT	40a380

(114) 0x40a3a0 LDR	X16, [X9, #32]

(114) 0x40a3a4 LDP	X16, X15, [X16, #32]

(114) 0x40a3a8 CMP	W14, #1

(114) 0x40a3ac B.NE	40a42c

(114) 0x40a3b0 ORR	W17, WZR, WZR

(114) 0x40a3b4 ORR	X18, XZR, X13

(114) 0x40a3b8 SUB	W14, W14, W17

(114) 0x40a3bc ADD	X17, X18, X18,LSL #1

(114) 0x40a3c0 ADD	X16, X16, X17,LSL #3

(114) 0x40a3c4 ADD	X15, X15, X17,LSL #3

(114) 0x40a3c8 ADD	X16, X16, #8

(114) 0x40a3cc ADD	X15, X15, #8

(114) 0x40a3d0 HINT	#0

(114) 0x40a3d4 HINT	#0

(114) 0x40a3d8 HINT	#0

(114) 0x40a3dc HINT	#0

  (115) 0x40a3e0 LDR	D0, [X19]

  (115) 0x40a3e4 LDUR	D1, [X15, #504]

  (115) 0x40a3e8 LDP	D2, D3, [X16, #1016]

  (115) 0x40a3ec SUBS	W14, W14, #1

  (115) 0x40a3f0 FMADD	D0, D1, D0, D2

  (115) 0x40a3f4 LDR	D2, [X16, #8]

  (115) 0x40a3f8 STUR	D0, [X16, #504]

  (115) 0x40a3fc LDR	D0, [X19]

  (115) 0x40a400 LDR	D1, [X15]

  (115) 0x40a404 FMADD	D0, D1, D0, D3

  (115) 0x40a408 STR	D0, [X16]

  (115) 0x40a40c LDR	D0, [X19]

  (115) 0x40a410 LDR	D1, [X15, #8]

  (115) 0x40a414 ADD	X15, X15, #24

  (115) 0x40a418 FMADD	D0, D1, D0, D2

  (115) 0x40a41c STR	D0, [X16, #8]

  (115) 0x40a420 ADD	X16, X16, #24

  (115) 0x40a424 B.NE	40a3e0

(114) 0x40a428 B	40a380

(114) 0x40a42c SUB	W0, W14, #1

(114) 0x40a430 ADD	X18, X13, W18,SXTW #1

(114) 0x40a434 ORR	W17, WZR, WZR

(114) 0x40a438 ADD	X0, X13, X0

(114) 0x40a43c ADD	X0, X0, X0,LSL #1

(114) 0x40a440 UBFM	X1, X18, #61, #60

(114) 0x40a444 ADD	X2, X16, X0,LSL #3

(114) 0x40a448 ADD	X0, X15, X0,LSL #3

(114) 0x40a44c ADD	X18, X16, X1

(114) 0x40a450 ADD	X0, X0, #24

(114) 0x40a454 ADD	X2, X2, #24

(114) 0x40a458 CMP	X18, X0

(114) 0x40a45c ADD	X0, X15, X1

(114) 0x40a460 CCMP	X0, X2, #2, #3

(114) 0x40a464 CSINC	W0, WZR, WZR, #2

(114) 0x40a468 CMP	X2, X19

(114) 0x40a46c CCMP	X18, X12, #2, #8

(114) 0x40a470 B.CC	40a3b4

(114) 0x40a474 ORR	X18, XZR, X13

(114) 0x40a478 TBNZ	W0, #0, 40a3b8

(114) 0x40a47c AND	X17, X14, #6015

(114) 0x40a480 ADD	X0, X16, X1

(114) 0x40a484 ADD	X1, X15, X1

(114) 0x40a488 ADD	X18, X17, X13

(114) 0x40a48c ORR	X2, XZR, X17

(114) 0x40a490 HINT	#0

(114) 0x40a494 HINT	#0

(114) 0x40a498 HINT	#0

(114) 0x40a49c HINT	#0

  (116) 0x40a4a0 LDR	D0, [X19]

  (116) 0x40a4a4 LD3	{V1.2D, V2.2D, V3.2D}, [X1], #80

  (116) 0x40a4a8 SUBS	X2, X2, #2

  (116) 0x40a4ac LD3	{V4.2D, V5.2D, V6.2D}, [X0]

  (116) 0x40a4b0 FMLA	V4.2D, V1.2D, V0.D[0]

  (116) 0x40a4b4 LDR	D0, [X19]

  (116) 0x40a4b8 FMLA	V5.2D, V2.2D, V0.D[0]

  (116) 0x40a4bc FMLA	V6.2D, V3.2D, V0.D[0]

  (116) 0x40a4c0 ST3	{V4.2D, V5.2D, V6.2D}, [X0], #48

  (116) 0x40a4c4 B.NE	40a4a0

(114) 0x40a4c8 CMP	X17, X14

(114) 0x40a4cc B.EQ	40a380

(114) 0x40a4d0 B	40a3b8

0x40a4d4 HINT	#0

0x40a4d8 HINT	#0

0x40a4dc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.00 to 3.10 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40a340 <advanceVelocity.omp_outlined+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f2e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3032	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W9, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W11, W9, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40a354 <advanceVelocity.omp_outlined+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40a340 <advanceVelocity.omp_outlined+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f2e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3032	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W9, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W11, W9, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40a354 <advanceVelocity.omp_outlined+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.82	0.19
▼Loop 114 - timestep.c:71-78 - exec–	0.02	0.01
○Loop 116 - timestep.c:76-78 - exec	1.72	0.18
○Loop 115 - timestep.c:74-78 - exec	0.09	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code