OV - exec - Function lcg61

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 48

--------------------------------------------------------------------------------

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

0x409df0 LDR	X8, [X0]

0x409df4 MOVZ	X9, #26389

0x409df8 MOVK	X9, #63861

0x409dfc MOVK	X9, #24685

0x409e00 MOVK	X9, #1555

0x409e04 MADD	X8, X8, X9, XZR

0x409e08 MOVZ	W9, #9

0x409e0c UMULH	X9, X8, X9

0x409e10 SUB	X10, X8, X9

0x409e14 ADD	X9, X9, X10,LSR #1

0x409e18 UBFM	X9, X9, #60, #63

0x409e1c SUB	X9, X9, X9,LSL #61

0x409e20 ADD	X8, X8, X9

0x409e24 UCVTF	D0, X8, #61

0x409e28 STR	X8, [X0]

0x409e2c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_5

Source file and lines	random.c:45-48
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-48.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 2.50 to 1.25 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00	0.00	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00	0.00	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.50 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 409df0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #26389	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #63861	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #24685	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #1555	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X8, X8, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MOVZ W9, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UMULH X9, X8, X9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	N/A
SUB X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X9, X10,LSR #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
UBFM X9, X9, #60, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X9, X9, X9,LSL #61	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UCVTF D0, X8, #61	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (50.0%)
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run armclang_5

Source file and lines	random.c:45-48
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-48.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 2.50 to 1.25 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

UCVTF: 1 occurrences►
- /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00	0.00	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	2.00	2.00	2.00	2.00	2.50	2.50	0.00	0.00	0.00	0.00	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.50 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 409df0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #26389	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #63861	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #24685	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVK X9, #1555	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD X8, X8, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MOVZ W9, #9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UMULH X9, X8, X9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	N/A
SUB X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X9, X10,LSR #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
UBFM X9, X9, #60, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SUB X9, X9, X9,LSL #61	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UCVTF D0, X8, #61	1	0	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (50.0%)
STR X8, [X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
○lcg61	0.02	0.00

Report Configuration

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code