OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:288-385 [...]	Coverage (incl. loops): 0.10% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 288 - 385

--------------------------------------------------------------------------------

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x407e30 STP	X29, X30, [SP, #960]!

0x407e34 STP	X24, X23, [SP, #16]

0x407e38 STP	X22, X21, [SP, #32]

0x407e3c STP	X20, X19, [SP, #48]

0x407e40 ADD	X29, SP, #0

0x407e44 LDR	W8, [X0, #12]

0x407e48 LDR	W9, [X0, #20]

0x407e4c ORR	X19, XZR, X1

0x407e50 ORR	X20, XZR, X0

0x407e54 CMP	W8, W9

0x407e58 B.GE	407e7c

0x407e5c LDR	X9, [X20, #120]

0x407e60 SBFM	X8, X8, #0, #31

(99) 0x407e64 STR	WZR, [X9, X8,LSL #2]

(99) 0x407e68 ADD	X8, X8, #1

(99) 0x407e6c LDRSW	X10, [X20, #20]

(99) 0x407e70 CMP	X8, X10

(99) 0x407e74 B.LT	407e64

0x407e78 LDR	W8, [X20, #12]

0x407e7c CMP	W8, #1

0x407e80 B.LT	407fa8

0x407e84 LDR	X9, [X20, #120]

0x407e88 MOVZ	W23, #24

0x407e8c ORR	X21, XZR, XZR

0x407e90 B	407eb0

0x407e94 HINT	#0

0x407e98 HINT	#0

0x407e9c HINT	#0

(97) 0x407ea0 LDR	W8, [X20, #12]

  (96) 0x407ea4 ADD	X21, X21, #1

  (96) 0x407ea8 CMP	X21, W8,SXTW

  (96) 0x407eac B.GE	407fa8

  (96) 0x407eb0 LDR	W10, [X9, X21,LSL #2]

  (96) 0x407eb4 CMP	W10, #1

  (96) 0x407eb8 B.LT	407ea4

(97) 0x407ebc ADD	X8, X21, X21,LSL #1

(97) 0x407ec0 ORR	W22, WZR, WZR

(97) 0x407ec4 UBFM	X24, X8, #55, #54

(97) 0x407ec8 B	407ee0

  (98) 0x407ecc ADD	W22, W22, #1

  (98) 0x407ed0 LDR	X9, [X20, #120]

  (98) 0x407ed4 LDR	W8, [X9, X21,LSL #2]

  (98) 0x407ed8 CMP	W22, W8

  (98) 0x407edc B.GE	407ea0

  (98) 0x407ee0 LDR	X8, [X19, #24]

  (98) 0x407ee4 LDR	D1, [X20, #48]

  (98) 0x407ee8 ADD	X8, X8, X24

  (98) 0x407eec SMADDL	X8, W22, W23, X8

  (98) 0x407ef0 LDR	D0, [X8]

  (98) 0x407ef4 FCMP	D0, D1

  (98) 0x407ef8 B.GE	407f24

  (98) 0x407efc LDR	D1, [X20, #24]

  (98) 0x407f00 LDR	W10, [X20]

  (98) 0x407f04 SUB	W11, W10, #1

  (98) 0x407f08 FSUB	D0, D0, S1

  (98) 0x407f0c LDR	D1, [X20, #96]

  (98) 0x407f10 FMUL	D0, D0, D1

  (98) 0x407f14 FCVTMS	W9, D0

  (98) 0x407f18 CMP	W10, W9

  (98) 0x407f1c CSEL	W1, W11, W9, #0

  (98) 0x407f20 B	407f28

  (98) 0x407f24 LDR	W1, [X20]

  (98) 0x407f28 LDP	D0, D1, [X8, #8]

  (98) 0x407f2c LDP	D2, D3, [X20, #32]

  (98) 0x407f30 LDP	D4, D5, [X20, #104]

  (98) 0x407f34 ORR	X0, XZR, X20

  (98) 0x407f38 FSUB	D3, D1, S3

  (98) 0x407f3c LDP	W9, W10, [X20, #4]

  (98) 0x407f40 SUB	W11, W9, #1

  (98) 0x407f44 FSUB	D2, D0, S2

  (98) 0x407f48 FMUL	D3, D3, D5

  (98) 0x407f4c FMUL	D2, D2, D4

  (98) 0x407f50 FCVTMS	W8, D2

  (98) 0x407f54 CMP	W9, W8

  (98) 0x407f58 CSEL	W8, W11, W8, #0

  (98) 0x407f5c FCVTMS	W11, D3

  (98) 0x407f60 LDP	D2, D3, [X20, #56]

  (98) 0x407f64 FCMP	D0, D2

  (98) 0x407f68 CSEL	W2, W8, W9, #11

  (98) 0x407f6c SUB	W8, W10, #1

  (98) 0x407f70 CMP	W10, W11

  (98) 0x407f74 CSEL	W8, W8, W11, #0

  (98) 0x407f78 FCMP	D1, D3

  (98) 0x407f7c CSEL	W3, W8, W10, #11

  (98) 0x407f80 BL	4079c0

  (98) 0x407f84 CMP	X21, W0,UXTW

  (98) 0x407f88 B.EQ	407ecc

  (98) 0x407f8c ORR	W4, WZR, W0

  (98) 0x407f90 ORR	X0, XZR, X20

  (98) 0x407f94 ORR	X1, XZR, X19

  (98) 0x407f98 ORR	W2, WZR, W22

  (98) 0x407f9c ORR	W3, WZR, W21

  (98) 0x407fa0 BL	407ca0

  (98) 0x407fa4 B	407ed0

0x407fa8 LDP	X20, X19, [SP, #48]

0x407fac LDP	X22, X21, [SP, #32]

0x407fb0 LDP	X24, X23, [SP, #16]

0x407fb4 LDP	X29, X30, [SP], #64

0x407fb8 RET

0x407fbc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.52+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.33 to 3.83 cycles (1.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 92 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	2.00	2.00	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

22% of peak load performance is reached (21.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W8, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407e7c <updateLinkCells+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 407fa8 <updateLinkCells+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W23, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 407eb0 <updateLinkCells+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 92 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00
cycles	2.00	2.00	1.50	1.50	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	4.33	4.33	4.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.13
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

22% of peak load performance is reached (21.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.77 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W8, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 407e7c <updateLinkCells+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X20, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 407fa8 <updateLinkCells+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W23, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 407eb0 <updateLinkCells+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.10	0.01
▼Loop 97 - linkCells.c:291-378 - exec–	0.00	0.00
○Loop 98 - linkCells.c:295-378 - exec	0.10	1.02
○Loop 96 - linkCells.c:291-295 - exec	0.00	0.01
○Loop 99 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

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Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code